Datasheet > CY62158DV30L

CY62158DV30L

更新时间： 2024-11-18 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	410K
描述
8-Mbit (1024K x 8) MoBL Static RAM

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CY62158DV30L 数据手册

CY62158DV30

MoBL^

8-Mbit (1024K x 8) MoBL^Static RAM

This is ideal for providing More Battery Life™ (MoBL^) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption by 85% when

deselected (CE₁HIGH or CE₂LOW).

Features

• Very high speed: 45 ns, 55 ns and 70 ns

— Wide voltage range: 2.20V – 3.60V

• Ultra-low active power

— Typical active current:1.5 mA @ f = 1 MHz

— Typical active current: 12 mA @ f = f_max

• Ultra-low standby power

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2

(CE₂) HIGH. Data on the eight I/O pins (I/O₀through I/O₇) is

then written into the location specified on the address pins (A₀

• Easy memory expansion with CE₁, CE₂, and OE

through A₁₉).

features

Reading from the device is accomplished by taking Chip

Enable 1 (CE₁) and Output Enable (OE) LOW and Chip

Enable 2 (CE₂) HIGH while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁

LOW and CE₂HIGH), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW and CE₂HIGH and WE

LOW). See the truth table for a complete description of read

and write modes.

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 48-ball BGA, 48-pin TSOPI, and

44-pin TSOPII

Functional Description^[1]

The CY62158DV30 is a high-performance CMOS static RAMs

organized as 1024K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

Logic Block Diagram

I/O

Data in Drivers

A₀

A₁

A₂

A₃

A₄

A⁵

A⁶

1024K x 8

A⁷

ARRAY

A₉⁸

A₁₀

A₁₁

A₁₂

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05391 Rev. *D

Revised June 17, 2004

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与CY62158DV30L相关器件

型号	品牌	获取价格	描述	数据表
CY62158DV30L-45BVI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM
CY62158DV30L-45ZSXI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM
CY62158DV30L-45ZXI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM
CY62158DV30L-55BVI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM
CY62158DV30L-55BVI	ROCHESTER	获取价格	暂无描述
CY62158DV30L-55BVIT	CYPRESS	获取价格	Standard SRAM, 1MX8, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62158DV30L-55ZSXI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM
CY62158DV30L-55ZSXI	ROCHESTER	获取价格	1MX8 STANDARD SRAM, 55ns, PDSO44, LEAD FREE, TSOP2-44
CY62158DV30L-55ZSXIT	CYPRESS	获取价格	暂无描述
CY62158DV30L-55ZXI	CYPRESS	获取价格	8-Mbit (1024K x 8) MoBL Static RAM

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