Datasheet > CY62157H30-45BVXA

CY62157H30-45BVXA

更新时间： 2024-11-19 14:54:19

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
18页	443K
描述
Asynchronous SRAM

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CY62157H30-45BVXA

Automotive

8-Mbit (512K Words × 16-Bit) Static RAM

with Error-Correcting Code (ECC)

8-Mbit (512K Words

× 16-Bit) Static RAM with Error-Correcting Code (ECC)

Devices with dual chip-enable are accessed by asserting both

chip-enable inputs – CE₁as LOW and CE₂as HIGH.

Features

■ AEC-Q100 Qualified

Data writes are performed by asserting the Write Enable input

(WE) LOW, and providing the data and address on device data

(I/O₀through I/O₁₅) and address (A₀through A₁₉) pins

respectively. The Byte High/Low Enable (BHE, BLE) inputs

control byte writes, and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O₈through

■ Ultra-low standby power

❐ Typical standby current: 5.5 μA

❐ Maximum standby current: 16 μA

■ High speed: 45 ns

■ Embedded error-correcting code (ECC) for single-bit error

correction

I/O₁₅; BLE controls I/O₀through I/O₇.

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on I/O lines (I/O₀through I/O₁₅). Byte

accesses can be performed by asserting the required byte

enable signal (BHE, BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ Temperature Ranges:

❐ Automotive-A: –40 °C to +85 °C

■ Operating voltage range: 2.2 V to 3.6 V

■ 1.0 V data retention

■ TTL-compatible inputs and outputs

■ Available in Pb-free 48-ball VFBGA package

All I/Os (I/O₀through I/O₁₅) are placed in a HI-Z state when the

device is deselected (CE₁HIGH / CE₂LOW for dual chip-enable

device), or control signals are de-asserted (OE, BLE, and BHE).

Functional Description

These devices also have a unique “Byte Power down” feature

where if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switches to standby mode irrespective of the

state of the chip enable(s), thereby saving power.

CY62157H30-45BVXA is high-performance CMOS low-power

(MoBL) SRAM device with embedded ECC. This device is

offered in dual chip-enable.

The logic block diagram is on page 2. Refer to Pin Configurations

on page 4 and the associated footnotes for details.

Product Portfolio

Power Dissipation

Speed

(ns)

Product

Range

V_CCRange (V)

Operating I_CC, (mA), f = f_max

Standby, I_SB2(µA)

Typ ^[2]

Max

Typ ^[2]

Max

CY62157H30-45BVXA Automotive-A

2.2 V–3.6 V

29.0

36.0

5.5

16.0

Note

1. This device does not support automatic write-back on error detection.

2. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested.

Cypress Semiconductor Corporation

Document Number: 002-19620 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 25, 2017

12 3 4 5 6 7...18

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与CY62157H30-45BVXA相关器件

型号	品牌	获取价格	描述	数据表
CY62157H30-45BVXAT	INFINEON	获取价格	Asynchronous SRAM
CY62157H30-45BVXI	CYPRESS	获取价格	8-Mbit (512K words Ã 16-bit) Static RAM with
CY62157H30-45BVXIT	CYPRESS	获取价格	8-Mbit (512K words Ã 16-bit) Static RAM with
CY62158CV25	CYPRESS	获取价格	1024K x 8 MoBL Static RAM
CY62158CV25LL-55BAI	ETC	获取价格	x8 SRAM
CY62158CV25LL-70BAI	CYPRESS	获取价格	1024K x 8 MoBL Static RAM
CY62158CV25LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 1MX8, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62158CV30	CYPRESS	获取价格	1024K x 8 MoBL Static RAM
CY62158CV30LL-55BAI	CYPRESS	获取价格	1024K x 8 MoBL Static RAM
CY62158CV30LL-70BAI	CYPRESS	获取价格	1024K x 8 MoBL Static RAM

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