Datasheet > 暂无类别数据> CY62147DV18LL-70BVIT

CY62147DV18LL-70BVIT

更新时间： 2024-11-19 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		内存集成电路静态存储器
页数	文件大小	规格书
11页	667K
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CY62147DV18

MoBL2™

4-Mb (256K x 16) Static RAM

mode reducing power consumption by more than 99% when

deselected (CE HIGH or both BLE and BHE are HIGH). The

input/output pins (I/O₀through I/O₁₅) are placed in a high-im-

pedance state when: deselected (CE HIGH), outputs are dis-

abled (OE HIGH), both Byte High Enable and Byte Low Enable

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW and WE LOW).

Writing to the device is accomplished by asserting Chip En-

able (CE) and Write Enable (WE) inputs LOW. If Byte Low

Enable (BLE) is LOW, then data from I/O pins (I/O₀through

I/O₇), is written into the location specified on the address pins

(A₀through A₁₇). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

Reading from the device is accomplished by asserting Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table for a complete description of read and write

modes.

Features

• Very high speed: 55 ns and 70 ns

• Wide voltage range: 1.65V – 2.25V

• Pin-compatible with CY62147CV18

• Ultra-low active power

— Typical active current: 1 mA @ f = 1 MHz

— Typical active current: 6 mA @ f = f_max

• Ultra low standby power

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered 48-ball BGA

Functional Description^[1]

The CY62147DV18 is a high-performance CMOS static RAM

organized as 256K words by 16 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL™) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

power consumption. The device can also be put into standby

The CY62147DV18 is available in a 48-ball FBGA package.

Logic Block Diagram

DATA IN DRIVERS

256K x 16

RAM Array

I/O – I/O

COLUMN DECODER

BHE

BLE

Power

Circuit

-Down

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05343 Rev. *B

Revised February 26, 2004

12 3 4 5 6 7...11

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与CY62147DV18LL-70BVIT相关器件

型号	品牌	获取价格	描述	数据表
CY62147DV18LL-70BVXI	CYPRESS	获取价格	4-Mb (256K x 16) Static RAM
CY62147DV18LL-70BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147DV30	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30_06	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30L	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30L-55BVI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30L-55BVI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30L-55BVIT	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30L-55BVXE	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30L-55BVXE	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

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