5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY62147DV30L-55BVXIT
CY62147DV30L-55BVXIT PDF预览

CY62147DV30L-55BVXIT

更新时间： 2024-11-19 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 393K
描述
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

阅读下载

中文翻译

获取价格

CY62147DV30L-55BVXIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.65
最长访问时间：55 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：8 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

CY62147DV30L-55BVXIT 数据手册

 浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第2页浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第3页浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第4页浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第5页浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第6页浏览型号CY62147DV30L-55BVXIT的Datasheet PDF文件第7页 
CY62147DV30  
4-Mbit (256K x 16) Static RAM  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
input/output pins (I/O0 through I/O15) are placed in a high-im-  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62147CV25, CY62147CV30, and  
CY62147CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Packages offered 48-ball BGA and 44-pin TSOPII  
• Also available in Lead-Free packages  
• Byte power-down feature  
Functional Description[1]  
The CY62147DV30 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications such as cellular telephones. The device also has  
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin  
TSOPII packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
256K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05340 Rev. *D  
Revised February 2, 2005  
1234567...12

中文翻译

下载PDF

与CY62147DV30L-55BVXIT相关器件

型号 品牌 获取价格 描述 数据表
CY62147DV30L-55ZSXE CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-55ZSXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVI ROCHESTER

获取价格

 		256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30L-70BVI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVXI ROCHESTER

获取价格

 		256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147DV30L-70ZSXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70ZSXI ROCHESTER

获取价格

 		256KX16 STANDARD SRAM, 70ns, PDSO44, LEAD FREE, TSOP2-44
CY62147DV30LL CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY62147DV30LL-45BVI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM

与CY62147DV30L-55BVXIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证