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CY62147DV18LL-70BVXIT PDF预览

CY62147DV18LL-70BVXIT

更新时间： 2024-11-19 21:04:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
11页 773K
描述
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

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CY62147DV18LL-70BVXIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.74
最长访问时间：70 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：8 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：2.25 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

CY62147DV18LL-70BVXIT 数据手册

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CY62147DV18  
MoBL2™  
4-Mb (256K x 16) Static RAM  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
input/output pins (I/O0 through I/O15) are placed in a high-im-  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Writing to the device is accomplished by asserting Chip En-  
able (CE) and Write Enable (WE) inputs LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Reading from the device is accomplished by asserting Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table for a complete description of read and write  
modes.  
Features  
• Very high speed: 55 ns and 70 ns  
• Wide voltage range: 1.65V – 2.25V  
• Pin-compatible with CY62147CV18  
• Ultra-low active power  
— Typical active current: 1 mA @ f = 1 MHz  
— Typical active current: 6 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered 48-ball BGA  
Functional Description[1]  
The CY62147DV18 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
The CY62147DV18 is available in a 48-ball FBGA package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
9
A
8
7
6
5
4
3
2
A
A
A
A
256K x 16  
RAM Array  
I/O – I/O  
0
7
A
I/O – I/O  
8
A
A
A
15  
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power  
Circuit  
-Down  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05343 Rev. *B  
Revised February 26, 2004  
[+] Feedback  
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