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CY62147DV30L-55ZSXI PDF预览

CY62147DV30L-55ZSXI

更新时间： 2024-11-19 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 393K
描述
4-Mbit (256K x 16) Static RAM

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中文翻译

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CY62147DV30L-55ZSXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：LEAD FREE, TSOP2-44针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.64最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e4长度：18.415 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.194 mm最大待机电流：0.000009 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.015 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：10.16 mmBase Number Matches：1

CY62147DV30L-55ZSXI 数据手册

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CY62147DV30  
4-Mbit (256K x 16) Static RAM  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
input/output pins (I/O0 through I/O15) are placed in a high-im-  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62147CV25, CY62147CV30, and  
CY62147CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Packages offered 48-ball BGA and 44-pin TSOPII  
• Also available in Lead-Free packages  
• Byte power-down feature  
Functional Description[1]  
The CY62147DV30 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications such as cellular telephones. The device also has  
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin  
TSOPII packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
256K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05340 Rev. *D  
Revised February 2, 2005  
1234567...12

中文翻译

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CY62147DV30L-70BVXI CYPRESS

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CY62147DV30LL-45BVXI ROCHESTER

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