Datasheet > CY62147EV18_10

CY62147EV18_10

更新时间： 2024-11-19 09:42:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	491K
描述
4-Mbit (256K x 16) Static RAM

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CY62147EV18_10 数据手册

CY62147EV18 MoBL^®

4-Mbit (256K x 16) Static RAM

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99% when deselected (CE HIGH or both BLE and BHE are

HIGH). The input and output pins (I/O₀through I/O₁₅) are placed

in a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), both the Byte High

Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),

or during an active write operation (CE LOW and WE LOW).

Features

■ Very high speed: 55 ns

■ Wide voltage range: 1.65 V to 2.25 V

■ Pin compatible with CY62147DV18

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A

■ Ultra low active power

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₇).

❐ Typical active current: 2 mA at f = 1 MHz

■ Ultra low standby power

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the “Truth Table” on page 10 for a

complete description of read and write modes.

■ Available in a Pb-free 48-ball very fine ball grid array (VFBGA)

package

Functional Description

The CY62147EV18 is a high performance CMOS static RAM

organized as 256 K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

256K x 16

I/O –I/O

RAM Array

I/O –I/O

COLUMN DECODER

BHE

POWER DOWN

CIRCUIT

BHE

BLE

Cypress Semiconductor Corporation

Document #: 38-05441 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

Revised October 06, 2010

•

408-943-2600

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与CY62147EV18_10相关器件

型号	品牌	获取价格	描述	数据表
CY62147EV18LL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147EV18LL-55BVX	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147EV18LL-55BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147EV18LL-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62147EV18LL-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62147EV30	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147EV30_09	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147EV30_11	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V
CY62147EV30_12	CYPRESS	获取价格	4-Mbit (256Kx16) Satic RAM
CY62147EV30_13	CYPRESS	获取价格	4-Mbit (256 K x 16) Static RAM

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