Datasheet > CY62147DV30LL

CY62147DV30LL

更新时间： 2024-11-19 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	393K
描述
4-Mbit (256K x 16) Static RAM

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CY62147DV30LL 数据手册

CY62147DV30

4-Mbit (256K x 16) Static RAM

an automatic power-down feature that significantly reduces

power consumption. The device can also be put into standby

mode reducing power consumption by more than 99% when

deselected (CE HIGH or both BLE and BHE are HIGH). The

input/output pins (I/O₀through I/O₁₅) are placed in a high-im-

pedance state when: deselected (CE HIGH), outputs are dis-

abled (OE HIGH), both Byte High Enable and Byte Low Enable

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW and WE LOW).

Features

• Very high speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Pin-compatible with CY62147CV25, CY62147CV30, and

CY62147CV33

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 8 mA @ f = f_max

• Ultra low standby power

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₇). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

• Packages offered 48-ball BGA and 44-pin TSOPII

• Also available in Lead-Free packages

• Byte power-down feature

Functional Description^[1]

The CY62147DV30 is a high-performance CMOS static RAM

organized as 256K words by 16 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has

The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin

TSOPII packages.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

256K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05340 Rev. *D

Revised February 2, 2005

12 3 4 5 6 7...12

中文翻译

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与CY62147DV30LL相关器件

型号	品牌	获取价格	描述	数据表
CY62147DV30LL-45BVI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30LL-45BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30LL-45BVXI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 45ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147DV30LL-45ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30LL-45ZSXI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 45ns, PDSO44, LEAD FREE, TSOP2-44
CY62147DV30LL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62147DV30LL-55BVI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62147DV30LL-55BVI	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30LL-55BVIT	ROCHESTER	获取价格	256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30LL-55BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM

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