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CY62147DV30L-55BVXE PDF预览

CY62147DV30L-55BVXE

更新时间： 2024-11-19 03:23:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 367K
描述
4-Mbit (256K x 16) Static RAM

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CY62147DV30L-55BVXE 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.62
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：256KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1 mm
最大待机电流：0.000015 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.015 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：6 mm
Base Number Matches：1

CY62147DV30L-55BVXE 数据手册

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CY62147DV30  
4-Mbit (256K x 16) Static RAM  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
input/output pins (I/O0 through I/O15) are placed in a high-im-  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Features  
• Temperature Ranges  
— Industrial: –40°C to +85°C  
— Automotive-A: –40°C to +85°C  
— Automotive-E: –40°C to +125°C  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62147CV25, CY62147CV30, and  
CY62147CV33  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Available in Pb-free and non Pb-free 48-ball VFBGA and  
non Pb-free 44-pin TSOPII  
• Byte power-down feature  
Functional Description[1]  
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin  
TSOPII packages.  
The CY62147DV30 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
7
6
A
A
A
A
256K x 16  
RAM Array  
5
4
3
2
I/O –I/O  
0
7
A
I/O –I/O  
A
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05340 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 31, 2006  
[+] Feedback  
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中文翻译

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CY62147DV30L-55BVXE 替代型号

型号 品牌 替代类型 描述 数据表
CY62147DV30LL-55BVXI CYPRESS

功能相似

 4-Mbit (256K x 16) Static RAM
CY62147DV30LL-55BVI CYPRESS

功能相似

 4-Mbit (256K x 16) Static RAM
CY62147DV30L-55BVI CYPRESS

功能相似

 4-Mbit (256K x 16) Static RAM

与CY62147DV30L-55BVXE相关器件

型号 品牌 获取价格 描述 数据表
CY62147DV30L-55BVXI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-55BVXIT CYPRESS

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 		Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147DV30L-55ZSXE CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-55ZSXI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVI ROCHESTER

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 		256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147DV30L-70BVI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVXI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70BVXI ROCHESTER

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 		256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147DV30L-70ZSXI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147DV30L-70ZSXI ROCHESTER

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 		256KX16 STANDARD SRAM, 70ns, PDSO44, LEAD FREE, TSOP2-44

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