Datasheet > CY62137FV30LL-55ZSXE

CY62137FV30LL-55ZSXE

更新时间： 2024-11-20 03:08:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	512K
描述
2-Mbit (128K x 16) Static RAM

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CY62137FV30 MoBL^®

2-Mbit (128K x 16) Static RAM

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption by 90% when addresses are not toggling. Placing

the device into standby mode reduces power consumption by

more than 99% when deselected (CE HIGH or both BLE and

BHE are HIGH). The input and output pins (IO₀through IO₁₅) are

placed in a high impedance state in the following conditions:

Features

■ Very high speed: 45 ns

■ Temperature ranges

❐ Industrial: –40°C to +85°C

❐ Automotive-A: –40°C to +85°C

❐ Automotive-E: –40°C to +125°C

■ Wide voltage range: 2.20V–3.60V

■ Deselected (CE HIGH)

■ Pin compatible with CY62137CV/CV25/CV30/CV33,

■ Outputs are disabled (OE HIGH)

CY62137V, and CY62137EV30

■ Both Byte High Enable and Byte Low Enable are disabled

■ Ultra low standby power

(BHE, BLE HIGH)

❐ Typical standby current: 1 µA

❐ Maximum standby current: 5 µA (Industrial)

■ Ultra low active power

■ Write operation is active (CE LOW and WE LOW)

Write to the device by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇) is written into the location

specified on the address pins (A₀through A₁₆). If Byte High

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

is written into the location specified on the address pins (A₀

❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)

■ Easy memory expansion with CE and OE features

)

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Byte power down feature

through A₁₆).

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 9 for a

complete description of read and write modes.

■ Available in Pb-free 48-Ball VFBGA and 44-pin TSOP II

package

Functional Description

The CY62137FV30 is a high performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

128K x 16

RAM Array

IO₀–IO₇

IO₈–IO₁₅

BHE

COLUMN DECODER

POWER DOWN

CIRCUIT

BLE

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-07141 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 03, 2007

12 3 4 5 6 7...12

中文翻译

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CY62137FV30LL-55ZSXE 替代型号

型号	品牌	替代类型	描述	数据表
CY62137FV30LL-55ZSXET	CYPRESS	完全替代	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

与CY62137FV30LL-55ZSXE相关器件

型号	品牌	获取价格	描述	数据表
CY62137FV30LL-55ZSXET	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62137FV30LL-55ZSXET	INFINEON	获取价格	Asynchronous SRAM
CY62137V	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137V_06	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137V18LL-70BAI	ETC	获取价格	x16 SRAM
CY62137VLL-55BAI	ETC	获取价格	x16 SRAM
CY62137VLL-55BAIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, FBGA-48
CY62137VLL-55ZI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VLL-55ZIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62137VLL-55ZXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM

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