CY62137FV30 MoBL®
2-Mbit (128K x 16) Static RAM
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input and output pins (IO0 through IO15) are
placed in a high impedance state in the following conditions:
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V–3.60V
■ Deselected (CE HIGH)
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
■ Outputs are disabled (OE HIGH)
CY62137V, and CY62137EV30
■ Both Byte High Enable and Byte Low Enable are disabled
■ Ultra low standby power
(BHE, BLE HIGH)
❐ Typical standby current: 1 µA
❐ Maximum standby current: 5 µA (Industrial)
■ Ultra low active power
■ Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
is written into the location specified on the address pins (A0
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
)
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
■ Available in Pb-free 48-Ball VFBGA and 44-pin TSOP II
package
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
128K x 16
RAM Array
IO0–IO7
IO8–IO15
BHE
WE
CE
COLUMN DECODER
CE
POWER DOWN
CIRCUIT
OE
BLE
BHE
BLE
Cypress Semiconductor Corporation
Document Number: 001-07141 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 03, 2007