5秒后页面跳转
捷配首页

Datasheet > CY62137VLL-55ZIT
CY62137VLL-55ZIT PDF预览

CY62137VLL-55ZIT

更新时间： 2024-11-06 10:29:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 277K
描述
Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, TSOP2-44

阅读下载

中文翻译

获取价格

CY62137VLL-55ZIT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2,
针数：44Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.82最长访问时间：55 ns
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
长度：18.415 mm内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：44字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.194 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：10.16 mm

CY62137VLL-55ZIT 数据手册

 浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第2页浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第3页浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第4页浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第5页浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第6页浏览型号CY62137VLL-55ZIT的Datasheet PDF文件第7页 
CY62137V MoBL®  
2-Mbit (128K x 16) Static RAM  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that reduces power  
consumption by 99% when addresses are not toggling. The  
device can also be put into standby mode when deselected  
(CE HIGH) or when CE is LOW and both BLE and BHE are  
HIGH. The input/output pins (I/O0 through I/O15) are placed in  
a high-impedance state when: deselected (CE HIGH), outputs  
are disabled (OE HIGH), BHE and BLE are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW, and WE  
LOW).  
Features  
• High Speed  
— 55 ns  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Wide voltage range: 2.7V – 3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
• Available in Pb-free and non Pb-free standard  
44-pin TSOP Type II package  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description[1]  
The CY62137V is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
Logic Block Diagram  
DATA IN DRIVERS  
10  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05051 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 19, 2006  
1234567...11

中文翻译

下载PDF

与CY62137VLL-55ZIT相关器件

型号 品牌 获取价格 描述 数据表
CY62137VLL-55ZXI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62137VLL-55ZXIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62137VLL-70BAI ETC

获取价格

 		x16 SRAM
CY62137VLL-70ZE CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZIT CYPRESS

获取价格

 		暂无描述
CY62137VLL-70ZSXE CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZSXET CYPRESS

获取价格

 		Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62137VLL-70ZXE CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZXI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM

与CY62137VLL-55ZIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证