CY62137VLL-70ZE

更新时间： 2024-11-04 22:23:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	215K
描述
2-Mbit (128K x 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62137VLL-70ZE 数据手册

CY62137V MoBL^

2-Mbit (128K x 16) Static RAM

also has an automatic power-down feature that reduces power

consumption by 99% when addresses are not toggling. The

device can also be put into standby mode when deselected

(CE HIGH) or when CE is LOW and both BLE and BHE are

HIGH. The input/output pins (I/O₀through I/O₁₅) are placed in

a high-impedance state when: deselected (CE HIGH), outputs

are disabled (OE HIGH), BHE and BLE are disabled (BHE,

BLE HIGH), or during a write operation (CE LOW, and WE

LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₆). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₆).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Features

• Temperature Ranges

—Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• High Speed: 55 ns and 70 ns

• Wide voltage range: 2.7V–3.6V

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Package Available in a standard 44-pin TSOP Type II

(forward pinout) package

Functional Description^[1]

The CY62137V is a high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life^®(MoBL^®) in

portable applications such as cellular telephones. The device

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

128K x 16

RAM Array

2048 x 1024

I/O₀– I/O₇

I/O₈– I/O₁₅

COLUMN DECODER

BHE

BLE

Power-down

Circuit

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05051 Rev. *B

Revised June 21, 2004

12 3 4 5 6 7...11

中文翻译

下载PDF

与CY62137VLL-70ZE相关器件

型号	品牌	获取价格	描述	数据表
CY62137VLL-70ZI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZIT	CYPRESS	获取价格	暂无描述
CY62137VLL-70ZSXE	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZSXET	CYPRESS	获取价格	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62137VLL-70ZXE	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VLL-70ZXIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62137VN	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VNLL-55ZXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137VNLL-70ZSXA	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM

与CY62137VLL-70ZE相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62137VLL-70ZE

CY62137VLL-70ZE 数据手册

与CY62137VLL-70ZE相关器件

与CY62137VLL-70ZE相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62137VLL-70ZE

CY62137VLL-70ZE 数据手册

与CY62137VLL-70ZE相关器件

与CY62137VLL-70ZE相关文章

您还可以找

您在本页遇到什么问题？