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CY62137VLL-70BAI

更新时间： 2024-11-04 23:45:07
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
11页 304K
描述
x16 SRAM

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中文翻译

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CY62137VLL-70BAI 数据手册

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1*CY62137V18  
MoBL2™  
CY62137V MoBL™  
128K x 16 Static RAM  
high-impedance state when: deselected (CE HIGH), outputs  
are disabled (OE HIGH), BHE and BLE are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW, and WE  
LOW).  
Features  
• Low voltage range:  
— CY62137V: 2.7V–3.6V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Functional Description  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The CY62137V is a high-performance CMOS static RAM or-  
ganized as 131,072 words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that reduces power con-  
sumption by 99% when addresses are not toggling. The device  
can also be put into standby mode when deselected (CE  
HIGH) or when CE is LOW and both BLE and BHE are HIGH.  
The input/output pins (I/O0 through I/O15) are placed in a  
The CY62137V is available in 48-ball FBGA and standard  
44-pin TSOP Type II (forward pinout) packaging.  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
A
2
7
9
OE  
A
A
1
8
BHE  
BLE  
I/O  
I/O  
14  
I/O  
A
0
A
7
6
5
CE  
A
A
A
A
128K x 16  
RAM Array  
I/O  
7
0
15  
37  
36  
35  
34  
33  
I/O –I/O  
I/O  
I/O  
8
0
7
1
2
4
9
13  
3
2
I/O –I/O  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
12  
8
15  
3
CC  
A
V
SS  
A
V
V
1
0
CC  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
A
4
5
6
7
11  
I/O  
10  
I/O  
I/O  
8
I/O  
I/O  
I/O  
14  
15  
16  
9
COLUMN DECODER  
WE 17  
NC  
18  
A
A
8
16  
19  
26  
25  
A
A
15  
14  
9
10  
11  
A
20  
21  
22  
A
A
BHE  
A
12  
24  
23  
WE  
CE  
OE  
13  
A
NC  
BLE  
CE  
Power Down  
Circuit  
BHE  
BLE  
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 2, 2001  
1234567...11

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