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CY62137VNLL-70ZSXA PDF预览

CY62137VNLL-70ZSXA

更新时间： 2024-11-05 03:07:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 468K
描述
2-Mbit (128K x 16) Static RAM

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CY62137VNLL-70ZSXA 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2, TSOP44,.46,32针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.74最长访问时间：70 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e4长度：18.415 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3/3.3 V认证状态：Not Qualified
座面最大高度：1.194 mm最大待机电流：0.0000075 A
最小待机电流：1 V子类别：SRAMs
最大压摆率：0.015 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：10.16 mmBase Number Matches：1

CY62137VNLL-70ZSXA 数据手册

 浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第2页浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第3页浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第4页浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第5页浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第6页浏览型号CY62137VNLL-70ZSXA的Datasheet PDF文件第7页 
CY62137VN MoBL®  
2-Mbit (128K x 16) Static RAM  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that reduces power  
consumption by 99% when addresses are not toggling. The  
device can also be put into standby mode when deselected  
(CE HIGH) or when CE is LOW and both BLE and BHE are  
HIGH. The input/output pins (I/O0 through I/O15) are placed in  
a high-impedance state when: deselected (CE HIGH), outputs  
are disabled (OE HIGH), BHE and BLE are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW, and WE  
LOW).Writing to the device is accomplished by taking Chip  
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).Reading from  
the device is accomplished by taking Chip Enable (CE) and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (BLE) is LOW, then data from the  
memory location specified by the address pins will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the truth table at the  
back of this data sheet for a complete description of read and  
write modes.  
Features  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• High Speed: 55 ns  
• Wide voltage range: 2.7V–3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free 44-pin TSOP Type II package  
Functional Description[1]  
The CY62137VN is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
Logic Block Diagram  
DATA IN DRIVERS  
10  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power-down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06497 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
[+] Feedback  
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