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CY62137VLL-70ZXIT

更新时间： 2024-11-05 20:56:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 277K
描述
Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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CY62137VLL-70ZXIT 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.77
最长访问时间：70 nsJESD-30 代码：R-PDSO-G44
JESD-609代码：e3/e4长度：18.415 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.194 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY62137VLL-70ZXIT 数据手册

 浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第2页浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第3页浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第4页浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第5页浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第6页浏览型号CY62137VLL-70ZXIT的Datasheet PDF文件第7页 
CY62137V MoBL®  
2-Mbit (128K x 16) Static RAM  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that reduces power  
consumption by 99% when addresses are not toggling. The  
device can also be put into standby mode when deselected  
(CE HIGH) or when CE is LOW and both BLE and BHE are  
HIGH. The input/output pins (I/O0 through I/O15) are placed in  
a high-impedance state when: deselected (CE HIGH), outputs  
are disabled (OE HIGH), BHE and BLE are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW, and WE  
LOW).  
Features  
• High Speed  
— 55 ns  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Wide voltage range: 2.7V – 3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
• Available in Pb-free and non Pb-free standard  
44-pin TSOP Type II package  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description[1]  
The CY62137V is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
Logic Block Diagram  
DATA IN DRIVERS  
10  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05051 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 19, 2006  
1234567...11

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