Datasheet > CY62138CV30

CY62138CV30

更新时间： 2024-11-04 22:24:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	236K
描述
2M (256K x 8) Static RAM

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CY62138CV30 数据手册

CY62138CV25/30/33 MoBL

CY62138CV MoBL

2M (256K x 8) Static RAM

bits. This device features advanced circuit design to provide

ultra-low active current. This is ideal for providing More Battery

Life™ (MoBL^®) in portable applications. The device also has

an automatic power-down feature that significantly reduces

power consumption by 80% when addresses are not toggling.

The device can be put into standby mode reducing power

consumption by more than 99% when deselected (CE₁HIGH

or CE₂LOW).

Features

• Very high speed: 55 ns and 70 ns

• Voltage range:

— CY62138CV25: 2.2V–2.7V

— CY62138CV30: 2.7V–3.3V

— CY62138CV33: 3.0V–3.6V

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2

(CE₂) HIGH. Data on the eight I/O pins (I/O₀through I/O₇) is

then written into the location specified on the address pins (A₀

through A₁₇).

— CY62138CV: 2.7V–3.6V

• Pin-compatible with CY62138V

• Ultra low active power

— Typical active current: 1.5 mA @ f = 1 MHz

Reading from the device is accomplished by taking Chip

Enable 1 (CE₁) and Output Enable (OE) LOW while forcing

Write Enable (WE) and Chip Enable 2 (CE₂) HIGH. Under

these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

— Typical active current: 5.5 mA @ f = f_max(70-ns

speed)

• Low standby power

• Easy memory expansion with CE₁, CE₂, and OE

features

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW, CE₂HIGH and WE LOW).

See the truth table at the back of this data sheet for a complete

description of read and write modes.

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 36-ball FBGA

Functional Description^[1]

The CY62138CV25/30/33 and CY62138CV are high-perfor-

mance CMOS static RAMs organized as 256K words by eight

Logic Block Diagram

I/O

Data in Drivers

256K x 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05200 Rev. *D

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised September 20, 2002

12 3 4 5 6 7...12

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与CY62138CV30相关器件

型号	品牌	获取价格	描述	数据表
CY62138CV30LL-55BAI	CYPRESS	获取价格	2M (256K x 8) Static RAM
CY62138CV30LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36
CY62138CV30LL-55BVI	CYPRESS	获取价格	2M (256K x 8) Static RAM
CY62138CV30LL-55BVIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
CY62138CV30LL-55BVXI	CYPRESS	获取价格	Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36
CY62138CV30LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36
CY62138CV30LL-70BAI	CYPRESS	获取价格	2M (256K x 8) Static RAM
CY62138CV30LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36
CY62138CV30LL-70BVI	CYPRESS	获取价格	2M (256K x 8) Static RAM
CY62138CV33	CYPRESS	获取价格	2M (256K x 8) Static RAM

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