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CY62138CV33LL-55BVIT PDF预览

CY62138CV33LL-55BVIT

更新时间： 2024-11-05 13:00:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 236K
描述
Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36

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CY62138CV33LL-55BVIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：36
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.78
Is Samacsys：N最长访问时间：55 ns
JESD-30 代码：R-PBGA-B36长度：8 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：8功能数量：1
端子数量：36字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX8封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：6 mm
Base Number Matches：1

CY62138CV33LL-55BVIT 数据手册

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®
®
CY62138CV25/30/33 MoBL  
CY62138CV MoBL  
2M (256K x 8) Static RAM  
bits. This device features advanced circuit design to provide  
ultra-low active current. This is ideal for providing More Battery  
Life™ (MoBL®) in portable applications. The device also has  
an automatic power-down feature that significantly reduces  
power consumption by 80% when addresses are not toggling.  
The device can be put into standby mode reducing power  
consumption by more than 99% when deselected (CE1 HIGH  
or CE2 LOW).  
Features  
• Very high speed: 55 ns and 70 ns  
• Voltage range:  
— CY62138CV25: 2.2V–2.7V  
— CY62138CV30: 2.7V–3.3V  
— CY62138CV33: 3.0V–3.6V  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is  
then written into the location specified on the address pins (A0  
through A17).  
— CY62138CV: 2.7V–3.6V  
• Pin-compatible with CY62138V  
• Ultra low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
— Typical active current: 5.5 mA @ f = fmax (70-ns  
speed)  
• Low standby power  
• Easy memory expansion with CE1, CE2, and OE  
features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH and WE LOW).  
See the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 36-ball FBGA  
Functional Description[1]  
The CY62138CV25/30/33 and CY62138CV are high-perfor-  
mance CMOS static RAMs organized as 256K words by eight  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
Data in Drivers  
A
0
A
1
A
2
3
4
A
A
A
5
A
256K x 8  
ARRAY  
6
A
7
A
8
A
9
A
10  
A
11  
6
7
POWER  
DOWN  
CE  
CE  
COLUMN  
DECODER  
1
2
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05200 Rev. *D  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised September 20, 2002  
1234567...12

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