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CY62137V18LL-70BAI PDF预览

CY62137V18LL-70BAI

更新时间： 2024-11-04 23:45:07
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
11页 259K
描述
x16 SRAM

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中文翻译

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CY62137V18LL-70BAI 数据手册

 浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第2页浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第3页浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第4页浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第5页浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第6页浏览型号CY62137V18LL-70BAI的Datasheet PDF文件第7页 
CY62137V MoBL™  
CY62137V18 MoBL2™  
128K x 16 Static RAM  
are placed in a high-impedance state when: deselected (CE  
HIGH), outputs are disabled (OE HIGH), BHE and BLE are  
disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
• Low voltage range:  
— CY62137V18: 1.65V–1.95V  
— CY62137V: 2.7V-3.6V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
• Ultra-low active, standby power  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
16  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
16  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
Functional Description  
The CY62137V and CY62137V18 are high-performance  
CMOS static RAMs organized as 131,072 words by 16 bits.  
This device features advanced circuit design to provide ul-  
tra-low active current. This is ideal for providing More Battery  
Life™ (MoBL™) in portable applications such as cellular tele-  
phones. The device also has an automatic power-down fea-  
ture that reduces power consumption by 99% when addresses  
are not toggling. The device can also be put into standby mode  
when deselected (CE HIGH) or when CE is LOW and both BLE  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
8
15  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The CY62137V and CY62137V18 are available in 48-ball  
FBGA and standard 44-pin TSOP Type II (forward pinout)  
packaging.  
and BHE are HIGH. The input/output pins (I/O through I/O  
)
0
15  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
A9  
A8  
A7  
A6  
A5  
A4  
2
7
OE  
A
1
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
CE  
128K x 16  
RAM Array  
I/O  
7
0
15  
37  
36  
35  
34  
33  
I/O0–I/O7  
I/O  
I/O  
8
1
2
14  
13  
12  
9
A3  
A2  
I/O8–I/O15  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
A1  
A0  
V
V
CC  
I/O  
32  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
9
8
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
16  
19  
A
A
15  
14  
9
10  
11  
A
20  
21  
22  
A
A
BHE  
A
12  
24  
23  
WE  
CE  
OE  
13  
A
NC  
BLE  
62137V–2  
CE  
Power Down  
Circuit  
BHE  
BLE  
62137V–1  
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
January 20, 2000  
1234567...11

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