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CY62137FV30LL-55ZSXET PDF预览

CY62137FV30LL-55ZSXET

更新时间： 2024-11-05 21:18:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 347K
描述
Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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中文翻译

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CY62137FV30LL-55ZSXET 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSOP2, TSOP44,.46,32
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.53
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e4
长度：18.415 mm内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：44字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：128KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.194 mm
最大待机电流：0.000012 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.025 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：10.16 mm
Base Number Matches：1

CY62137FV30LL-55ZSXET 数据手册

 浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第2页浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第3页浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第4页浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第5页浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第6页浏览型号CY62137FV30LL-55ZSXET的Datasheet PDF文件第7页 
CY62137FV30 MoBL®Automotive  
2-Mbit (128 K × 16) Static RAM  
2-Mbit (128  
K × 16) Static RAM  
Features  
Functional Description  
■ Very high speed: 45 ns  
The CY62137FV30 is a high performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99% when deselected (CE HIGH or both BLE and BHE are  
HIGH). The input and output pins (I/O0 through I/O15) are placed  
in a high impedance state in the following conditions when the  
device is deselected (CE HIGH), the outputs are disabled (OE  
HIGH), both the Byte High Enable and the Byte Low Enable are  
disabled (BHE, BLE HIGH), or during an active write operation  
(CE LOW and WE LOW).  
■ Temperature ranges  
❐ Automotive-A: –40 °C to +85 °C  
❐ Automotive-E: –40 °C to +125 °C  
■ Wide voltage range: 2.20 V–3.60 V  
■ Pin  
compatible  
with  
CY62137CV/CV25/CV30/CV33,  
CY62137V, and CY62137EV30  
■ Ultra low standby power  
❐ Typical standby current: 1 A (Automotive-A)  
❐ Maximum standby current: 5 A (Automotive-A)  
■ Ultra low active power  
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)  
■ Easy memory expansion with CE and OE features  
■ Automatic power down when deselected  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A16). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A16).  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
■ Byte power down feature  
■ Available in 44-pin thin small outline package (TSOP) II  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the Truth Table on page 11 for a  
complete description of read and write modes.  
package  
For a complete list of related resources, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
BHE  
WE  
CE  
COLUMN DECODER  
CE  
POWER DOWN  
CIRCUIT  
OE  
BLE  
BHE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-66190 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 3, 2018  
 
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中文翻译

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CY62137FV30LL-55ZSXET 替代型号

型号 品牌 替代类型 描述 数据表
CY62137FV30LL-55ZSXE CYPRESS

完全替代

 2-Mbit (128K x 16) Static RAM

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CY62137VLL-55ZIT CYPRESS

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