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CY62128DV30LL-70ZI PDF预览

CY62128DV30LL-70ZI

更新时间： 2024-02-28 20:54:01
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 198K
描述
1 Mb (128K x 8) Static RAM

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中文翻译

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CY62128DV30LL-70ZI 技术参数

生命周期：Active零件包装代码：TSOP1
包装说明：8 X 20 MM, LEAD FREE, TSOP1-32针数：32
Reach Compliance Code：unknown风险等级：5.64
最长访问时间：70 nsJESD-30 代码：R-PDSO-G32
JESD-609代码：e3长度：18.4 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：8功能数量：1
端子数量：32字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：COMMERCIAL座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：8 mmBase Number Matches：1

CY62128DV30LL-70ZI 数据手册

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CY62128DV30  
MoBL  
1 Mb (128K x 8) Static RAM  
power consumption by 90% when addresses are not toggling.  
The device can be put into standby mode reducing power con-  
sumption by more than 99% when deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output  
pins (I/O0 through I/O7) are placed in a high-impedance state  
when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable  
2 (CE2) LOW, outputs are disabled (OE HIGH), or during a  
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2  
(CE2) HIGH and Write Enable (WE) LOW).  
Features  
• Very high speed: 55 and 70 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62128V  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write En-  
able(WE) LOW. Data on the eight I/O pins is then written into  
the location specified on the Address pin (A0 thro. A16).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a  
32-lead Short TSOP, and a 32-lead Reverse TSOP  
Reading from the device is accomplished by taking Chip En-  
able 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
Functional Description[1]  
The CY62128DV30 is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
The eight input/output pins (I/Oo through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or  
during a write operation (CE1 LOW, CE2 HIGH), and WE  
LOW).  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
Data in Drivers  
A
A
A
A
A
A
0
1
2
3
4
5
6
7
A
128K x 8  
ARRAY  
A
A
A
A10  
A11  
8
9
Power-  
down  
CE  
CE  
COLUMN  
DECODER  
1
2
I/O  
WE  
OE  
7
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05231 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 29, 2003  
1234567...11

中文翻译

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CY62128DV30LL-70ZI 替代型号

型号 品牌 替代类型 描述 数据表
CY62128EV30LL-45ZXI CYPRESS

类似代替

 1 Mbit (128K x 8) Static RAM
K6X1008T2D-TF70 SAMSUNG

功能相似

 128Kx8 bit Low Power CMOS Static RAM

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