Datasheet > CY62128ELL-45ZXI

CY62128ELL-45ZXI

更新时间： 2023-12-06 19:51:41

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	907K
描述
Asynchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62128ELL-45ZXI 数据手册

CY62128E MoBL^®

1-Mbit (128 K × 8) Static RAM

1-Mbit (128

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

The CY62128E is a high performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications. The device also has an automatic power down

feature that significantly reduces power consumption when

addresses are not toggling. Placing the device into standby

mode reduces power consumption by more than 99 percent

when deselected (CE₁HIGH or CE₂LOW). The eight input and

output pins (I/O₀through I/O₇) are placed in a high impedance

state when the device is deselected (CE₁HIGH or CE₂LOW),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE₁LOW and CE₂HIGH and WE LOW).

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

❐ Automotive-A: –40 °C to +85 °C

❐ Automotive-E: –40 °C to +125 °C

■ Voltage range: 4.5 V to 5.5 V

■ Pin compatible with CY62128B

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 4 A (Industrial)

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₆).

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic power down when deselected

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and

32-pin thin small outline package (TSOP) Type I packages

The CY62128E device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see Electrical Characteristics

on page 5 for more details and suggested alternatives.

For a complete list of related resources, click here.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

128K x 8

ARRAY

I/O

POWER

DOWN

I/O

COLUMN DECODER

Cypress Semiconductor Corporation

Document Number: 38-05485 Rev. *P

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 4, 2017

12 3 4 5 6 7...20

中文翻译

下载PDF

与CY62128ELL-45ZXI相关器件

型号	品牌	获取价格	描述	数据表
CY62128ELL-45ZXIT	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Static RAM
CY62128ELL-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-55SXE	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-55SXE	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-55SXET	CYPRESS	获取价格	暂无描述
CY62128ELL-55SXET	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-55ZAXE	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-55ZAXE	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-55ZAXET	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32,
CY62128ELL-55ZAXET	INFINEON	获取价格	Asynchronous SRAM

与CY62128ELL-45ZXI相关文章

LTM4644/LTM4644-1：创新的四输出同步降压微模块调节器
2024-07-02

2
2N3500：一款多用途NPN硅晶体管的全面解析
2024-07-02

2
最详细资料解析：BA5917AFP参数说明、引脚说明
2024-07-02

4
MAX232IDR数据手册：产品特性、电气参数、替代型号推荐
2024-07-02

1

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62128ELL-45ZXI

CY62128ELL-45ZXI 数据手册

与CY62128ELL-45ZXI相关器件

与CY62128ELL-45ZXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62128ELL-45ZXI

CY62128ELL-45ZXI 数据手册

与CY62128ELL-45ZXI相关器件

与CY62128ELL-45ZXI相关文章

您还可以找

您在本页遇到什么问题？