Datasheet > CY62128EV30_1106

CY62128EV30_1106

更新时间： 2024-01-15 06:33:08

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	952K
描述
1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected

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中文翻译

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CY62128EV30_1106 数据手册

CY62128EV30 MoBL^®

1-Mbit (128 K × 8) Static RAM

1-Mbit (128

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

The CY62128EV30 is a high performance CMOS static RAM

module organized as 128K words by 8-bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power-down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device in standby mode reduces power consumption by more

than 99 percent when deselected (CE₁HIGH or CE₂LOW). The

eight input and output pins (I/O₀through I/O₇) are placed in a

high impedance state when the device is deselected (CE₁HIGH

or CE₂LOW), the outputs are disabled (OE HIGH), or a write

operation is in progress (CE₁LOW and CE₂HIGH and WE

LOW).

■ Temperature ranges:

❐ Industrial: –40 °C to +85 °C

■ Wide voltage range: 2.2 V to 3.6 V

■ Pin compatible with CY62128DV30

■ Ultra low standby power

❐ Typical standby current: 1 µA

❐ Maximum standby current: 4 µA

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic power-down when deselected

To write to the device, take chip enable (CE₁LOW and CE₂

HIGH) and write enable (WE) inputs LOW. Data on the eight I/O

pins is then written into the location specified on the address pin

(A₀through A₁₆).

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

To read from the device, take chip enable (CE₁LOW and CE₂

HIGH) and output enable (OE) LOW while forcing write enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Offered in Pb-free 32-pin SOIC, 32-pin thin small outline

package (TSOP) Type I, and 32-pin shrunk thin small outline

package (STSOP) packages

Logic Block Diagram

I/O

INPUT BUFFER

I/O

128K x 8

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Cypress Semiconductor Corporation

Document #: 38-05579 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 25, 2011

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与CY62128EV30_1106相关器件

型号	品牌	获取价格	描述	数据表
CY62128EV30LL	CYPRESS	获取价格	1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected
CY62128EV30LL-45SXA	CYPRESS	获取价格	1 Mbit (128K x 8) Static RAM
CY62128EV30LL-45SXAD	CYPRESS	获取价格	Standard SRAM,
CY62128EV30LL-45SXAT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOIC-32
CY62128EV30LL-45SXI	CYPRESS	获取价格	1 Mbit (128K x 8) Static RAM
CY62128EV30LL-45SXI	INFINEON	获取价格	Asynchronous SRAM
CY62128EV30LL-45SXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128EV30LL-45SXIT	INFINEON	获取价格	Asynchronous SRAM
CY62128EV30LL-45ZAXA	CYPRESS	获取价格	暂无描述
CY62128EV30LL-45ZAXAT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32

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