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CY62128EV30LL-45ZAXA

更新时间： 2024-01-16 13:29:22
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
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CY62128EV30LL-45ZAXA 数据手册

 浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第2页浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第3页浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第4页浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第5页浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第6页浏览型号CY62128EV30LL-45ZAXA的Datasheet PDF文件第7页 
CY62128EV30 MoBL®  
1 Mbit (128K x 8) Static RAM  
Features  
Functional Description  
■ Very High Speed: 45 ns  
The CY62128EV30[1] is a high performance CMOS static RAM  
module organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The  
eight input and output pins (I/O0 through I/O7) are placed in a  
high impedance state when the device is deselected (CE1 HIGH  
or CE2 LOW), the outputs are disabled (OE HIGH), or a write  
operation is in progress (CE1 LOW and CE2 HIGH and WE  
LOW).  
■ Temperature Ranges:  
❐ Industrial: –40°C to +85°C  
❐ Automotive-A: –40°C to +85°C  
❐ Automotive-E: –40°C to +125°C  
■ Wide Voltage Range: 2.2 V to 3.6 V  
■ Pin Compatible with CY62128DV30  
■ Ultra Low Standby Power  
❐ Typical standby current: 1 μA  
❐ Maximum standby current: 4 μA  
■ Ultra Low Active Power  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins is then written into the location specified on the Address pin  
(A0 through A16).  
❐ Typical active current: 1.3 mA @ f = 1 MHz  
■ Easy Memory Expansion with CE1, CE2 and OE Features  
■ Automatic Power Down when Deselected  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
■ CMOS for Optimum Speed and Power  
■ Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin  
STSOP Packages  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
1
IO  
2
128K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05579 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 05, 2009  
[+] Feedback  
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CY62128EV30LL-45ZAXA 替代型号

型号 品牌 替代类型 描述 数据表
CY62128EV30LL-45ZAXAT CYPRESS

完全替代

 Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62128EV30LL-45ZAXI CYPRESS

完全替代

 1 Mbit (128K x 8) Static RAM

与CY62128EV30LL-45ZAXA相关器件

型号 品牌 获取价格 描述 数据表
CY62128EV30LL-45ZAXAT CYPRESS

获取价格

 		Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62128EV30LL-45ZAXI CYPRESS

获取价格

 		1 Mbit (128K x 8) Static RAM
CY62128EV30LL-45ZAXI INFINEON

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 		Asynchronous SRAM
CY62128EV30LL-45ZAXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62128EV30LL-45ZXA CYPRESS

获取价格

 		1 Mbit (128K x 8) Static RAM
CY62128EV30LL-45ZXAT CYPRESS

获取价格

 		Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128EV30LL-45ZXI CYPRESS

获取价格

 		1 Mbit (128K x 8) Static RAM
CY62128EV30LL-45ZXI INFINEON

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 		Asynchronous SRAM
CY62128EV30LL-45ZXIT CYPRESS

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 		1-Mbit (128 K x 8) Static RAM
CY62128EV30LL-45ZXIT INFINEON

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 		Asynchronous SRAM

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