CY62128EV30 MoBL®
1-Mbit (128K × 8) Static RAM
1-Mbit (128K
× 8) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The
eight input and output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE1 HIGH
or CE2 LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW).
■ Temperature ranges:
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62128DV30
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 4 µA
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power-down when deselected
To write to the device, take chip enable (CE1 LOW and CE2
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A0 through A16).
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
To read from the device, take chip enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ OfferedinPb-free32-pinsmalloutlineintegratedcircuit(SOIC),
32-pin thin small outline package (TSOP) Type I, and 32-pin
shrunk thin small outline package (STSOP) packages
For a complete list of related resources, click here.
Logic Block Diagram
I/O
0
INPUT BUFFER
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
I/O
1
I/O
2
128K x 8
ARRAY
I/O
3
I/O
I/O
I/O
I/O
4
5
6
7
A
A
A
9
10
11
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Cypress Semiconductor Corporation
Document Number: 38-05579 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 22, 2016