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CY62128EV30LL-55SXET PDF预览

CY62128EV30LL-55SXET

更新时间： 2024-09-28 20:10:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
19页 374K
描述
SRAM,

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中文翻译

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CY62128EV30LL-55SXET 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.84
Base Number Matches：1

CY62128EV30LL-55SXET 数据手册

 浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第2页浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第3页浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第4页浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第5页浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第6页浏览型号CY62128EV30LL-55SXET的Datasheet PDF文件第7页 
CY62128EV30 MoBL® Automotive  
1-Mbit (128 K × 8) Static RAM  
1-Mbit (128  
K × 8) Static RAM  
Features  
Functional Description  
■ Very high-speed: 45 ns  
The CY62128EV30 is a high performance CMOS static RAM  
module organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power-down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device in standby mode reduces power consumption by more  
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The  
eight input and output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1 HIGH  
or CE2 LOW), the outputs are disabled (OE HIGH), or a write  
operation is in progress (CE1 LOW and CE2 HIGH and WE  
LOW).  
■ Temperature ranges:  
❐ Automotive-A: –40 °C to +85 °C  
❐ Automotive-E: –40 °C to +125 °C  
■ Wide voltage range: 2.2 V to 3.6 V  
■ Pin compatible with CY62128DV30  
■ Ultra low standby power  
❐ Typical standby current: 1 A  
❐ Maximum standby current: 4 A  
■ Ultra low active power  
❐ Typical active current: 1.3 mA at f = 1 MHz  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins is then written into the location specified on the Address pin  
(A0 through A16).  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
■ OfferedinPb-free32-pinsmalloutlineintegratedcircuit(SOIC),  
32-pin thin small outline package (TSOP) Type I, and 32-pin  
STSOP packages  
For a complete list of related resources, click here.  
Logic Block Diagram  
I/O  
0
INPUT BUFFER  
A
0
A
1
I/O  
1
A
2
A
3
I/O  
2
A
4
A
A
A
A
A
A
A
128K x 8  
ARRAY  
I/O  
3
5
6
I/O  
I/O  
I/O  
I/O  
7
4
5
6
7
8
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 001-65528 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 15, 2015  
 
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