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CY62128ELL-55SXET

更新时间： 2024-01-30 07:28:01
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赛普拉斯 - CYPRESS /
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CY62128ELL-55SXET 数据手册

 浏览型号CY62128ELL-55SXET的Datasheet PDF文件第2页浏览型号CY62128ELL-55SXET的Datasheet PDF文件第3页浏览型号CY62128ELL-55SXET的Datasheet PDF文件第4页浏览型号CY62128ELL-55SXET的Datasheet PDF文件第5页浏览型号CY62128ELL-55SXET的Datasheet PDF文件第6页浏览型号CY62128ELL-55SXET的Datasheet PDF文件第7页 
MoBL® CY62128E  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description  
■ Very high speed: 45 ns  
The CY62128E[1] is a high performance CMOS static RAM  
organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The  
eight input and output pins (IO0 through IO7) are placed in a high  
impedance state when the device is deselected (CE1 HIGH or  
CE2 LOW), the outputs are disabled (OE HIGH), or a write  
operation is in progress (CE1 LOW and CE2 HIGH and WE LOW)  
■ Temperature ranges  
❐ Industrial: –40°C to +85°C  
❐ Automotive-A: –40°C to +85°C  
❐ Automotive-E: –40°C to +125°C  
■ Voltage range: 4.5V to 5.5V  
■ Pin compatible with CY62128B  
■ Ultra low standby power  
❐ Typical standby current: 1 μA  
❐ Maximum standby current: 4 μA (Industrial)  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO  
pins (IO0 through IO7) is then written into the location specified  
on the address pins (A0 through A16).  
■ Ultra low active power  
❐ Typical active current: 1.3 mA at f = 1 MHz  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the IO pins.  
■ CMOS for optimum speed and power  
■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and  
32-pin TSOP I packages  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
A
0
A
1
IO  
1
A
2
A
3
IO  
2
A
4
A
A
A
A
A
A
A
128K x 8  
ARRAY  
IO  
3
5
6
IO  
IO  
IO  
IO  
7
4
5
6
7
8
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05485 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 4, 2008  
[+] Feedback  
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CY62128ELL-55SXET 替代型号

型号 品牌 替代类型 描述 数据表
CY62128ELL-55SXE CYPRESS

完全替代

 1-Mbit (128K x 8) Static RAM

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