Datasheet > CY62128E_13

CY62128E_13

更新时间： 2024-01-11 02:26:33

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	970K
描述
1-Mbit (128 K x 8) Static RAM

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中文翻译

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CY62128E_13 数据手册

CY62128E MoBL^®

1-Mbit (128 K × 8) Static RAM

1-Mbit (128

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

The CY62128E is a high performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications. The device also has an automatic power down

feature that significantly reduces power consumption when

addresses are not toggling. Placing the device into standby

mode reduces power consumption by more than 99 percent

when deselected (CE₁HIGH or CE₂LOW). The eight input and

output pins (I/O₀through I/O₇) are placed in a high impedance

state when the device is deselected (CE₁HIGH or CE₂LOW),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE₁LOW and CE₂HIGH and WE LOW)

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

❐ Automotive-A: –40 °C to +85 °C

❐ Automotive-E: –40 °C to +125 °C

■ Voltage range: 4.5 V to 5.5 V

■ Pin compatible with CY62128B

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 4 A (Industrial)

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₆).

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic power down when deselected

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and

32-pin thin small outline package (TSOP) Type I packages

The CY62128E device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see Electrical Characteristics

on page 5 for more details and suggested alternatives.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

128K x 8

ARRAY

I/O

POWER

DOWN

I/O

COLUMN DECODER

Cypress Semiconductor Corporation

Document Number: 38-05485 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 3, 2013

12 3 4 5 6 7...19

中文翻译

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与CY62128E_13相关器件

型号	品牌	获取价格	描述	数据表
CY62128ELL	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXA	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXA	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXAT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32,
CY62128ELL-45SXAT	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXI	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, PLASTIC, SOIC-32
CY62128ELL-45SXIT	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45ZAXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM

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