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CY62128ELL-45ZAXIT PDF预览

CY62128ELL-45ZAXIT

更新时间: 2024-02-01 03:24:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
20页 803K
描述
Standard SRAM, 128KX8, 45ns, CMOS, PDSO32,

CY62128ELL-45ZAXIT 技术参数

生命周期:Active包装说明:TSSOP,
Reach Compliance Code:unknown风险等级:5.79
最长访问时间:45 ns长度:11.8 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装代码:TSSOP并行/串行:PARALLEL
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
技术:CMOS温度等级:INDUSTRIAL
端子面层:NOT SPECIFIED端子节距:0.5 mm
宽度:8 mmBase Number Matches:1

CY62128ELL-45ZAXIT 数据手册

 浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第2页浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第3页浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第4页浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第5页浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第6页浏览型号CY62128ELL-45ZAXIT的Datasheet PDF文件第7页 
CY62128E MoBL®  
1-Mbit (128 K × 8) Static RAM  
1-Mbit (128  
K × 8) Static RAM  
Features  
Functional Description  
Very high speed: 45 ns  
The CY62128E is a high performance CMOS static RAM  
organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications. The device also has an automatic power down  
feature that significantly reduces power consumption when  
addresses are not toggling. Placing the device into standby  
mode reduces power consumption by more than 99 percent  
when deselected (CE1 HIGH or CE2 LOW). The eight input and  
output pins (I/O0 through I/O7) are placed in a high impedance  
state when the device is deselected (CE1 HIGH or CE2 LOW),  
the outputs are disabled (OE HIGH), or a write operation is in  
progress (CE1 LOW and CE2 HIGH and WE LOW).  
Temperature ranges  
Industrial: –40 °C to +85 °C  
Automotive-A: –40 °C to +85 °C  
Automotive-E: –40 °C to +125 °C  
Voltage range: 4.5 V to 5.5 V  
Pin compatible with CY62128B  
Ultra low standby power  
Typical standby current: 1 A  
Maximum standby current: 4 A (Industrial)  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location specified  
on the address pins (A0 through A16).  
Ultra low active power  
Typical active current: 1.3 mA at f = 1 MHz  
Easy memory expansion with CE1, CE2, and OE features  
Automatic power down when deselected  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and  
32-pin thin small outline package (TSOP) Type I packages  
The CY62128E device is suitable for interfacing with processors  
that have TTL I/P levels. It is not suitable for processors that  
require CMOS I/P levels. Please see Electrical Characteristics  
on page 5 for more details and suggested alternatives.  
For a complete list of related resources, click here.  
Logic Block Diagram  
I/O  
0
INPUT BUFFER  
A
0
I/O  
A
1
1
A
2
I/O  
A
3
2
A
4
A
A
A
A
A
A
A
128K x 8  
ARRAY  
I/O  
3
5
6
I/O  
7
4
8
I/O  
9
5
10  
11  
I/O  
6
CE  
CE  
1
2
POWER  
DOWN  
I/O  
COLUMN DECODER  
7
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 38-05485 Rev. *P  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 4, 2017  
 

CY62128ELL-45ZAXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62128ELL-45ZAXI CYPRESS

完全替代

1-Mbit (128K x 8) Static RAM

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