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CY62128DV30LL-70ZXIT PDF预览

CY62128DV30LL-70ZXIT

更新时间： 2024-01-14 00:53:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 578K
描述
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32

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CY62128DV30LL-70ZXIT 技术参数

生命周期：Obsolete零件包装代码：TSOP1
包装说明：TSOP1,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.39最长访问时间：70 ns
JESD-30 代码：R-PDSO-G32JESD-609代码：e3
长度：18.4 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：32
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：8 mm
Base Number Matches：1

CY62128DV30LL-70ZXIT 数据手册

 浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第2页浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第3页浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第4页浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第5页浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第6页浏览型号CY62128DV30LL-70ZXIT的Datasheet PDF文件第7页 
CY62128DV30  
1-Mb (128K x 8) Static RAM  
also has an automatic power-down feature that significantly  
reduces power consumption by 90% when addresses are not  
toggling. The device can be put into standby mode reducing  
power consumption by more than 99% when deselected Chip  
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The  
input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when: deselected Chip Enable 1 (CE1)  
HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE  
HIGH), or during a write operation (Chip Enable 1 (CE1) LOW  
and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW).  
Features  
• Very high speed: 55 and 70 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62128V  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) LOW. Data on the eight I/O pins is then written into the  
location specified on the Address pin (A0 through A16).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. Under these conditions, the contents of the memory  
location specified by the address pins will appear on the I/O  
pins.  
• Available in Pb-free and non Pb-free 32-lead SOIC,  
32-lead TSOP and 32-lead Small TSOP, non Pb-free  
32-lead Reverse TSOP packages  
Functional Description[1]  
The eight input/output pins (I/Oo through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or  
during a write operation (CE1 LOW, CE2 HIGH), and WE  
LOW).  
The CY62128DV30 is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
I/O  
0
Data in Drivers  
A
A
A
A
A
A
A
A
A
A
I/O  
0
1
2
3
4
5
6
7
8
9
1
I/O  
2
I/O  
3
128K x 8  
ARRAY  
I/O  
4
A10  
A11  
I/O  
5
I/O  
6
Power-  
down  
CE  
CE  
COLUMN  
DECODER  
1
2
I/O  
WE  
OE  
7
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05231 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 19, 2006  
1234567...11

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