Datasheet > CY62128E

CY62128E

更新时间： 2024-02-02 11:46:26

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	948K
描述
1-Mbit (128K x 8) Static RAM

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CY62128E 数据手册

CY62128E MoBL^®

1-Mbit (128K x 8) Static RAM

Features

Functional Description^[1]

The CY62128E is a high performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE₁HIGH

or CE₂LOW). The eight input and output pins (IO₀through

IO₇) are placed in a high impedance state when the device is

deselected (CE₁HIGH or CE₂LOW), the outputs are disabled

(OE HIGH), or a write operation is in progress (CE₁LOW and

CE₂HIGH and WE LOW)

• Very high speed: 45 ns

• Temperature ranges

— Industrial: –40°C to +85°C

— Automotive-A: –40°C to +85°C

— Automotive-E: –40°C to +125°C

• Voltage range: 4.5V–5.5V

• Pin compatible with CY62128B

• Ultra low standby power

— Typical standby current: 1 µA

— Maximum standby current: 4 µA (Industrial)

• Ultra low active power

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight

IO pins (IO₀through IO₇) is then written into the location

specified on the address pins (A₀through A₁₆).

— Typical active current: 1.3 mA @ f = 1 MHz

• Easy memory expansion with CE₁, CE₂and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins appears on

the IO pins.

• Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC,

and 32-pin TSOP I packages

Logic Block Diagram

INPUT BUFFER

128K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05485 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 07, 2007

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与CY62128E相关器件

型号	品牌	获取价格	描述	数据表
CY62128E_09	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128E_13	CYPRESS	获取价格	1-Mbit (128 K x 8) Static RAM
CY62128ELL	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXA	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXA	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXAT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32,
CY62128ELL-45SXAT	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY62128ELL-45SXI	INFINEON	获取价格	Asynchronous SRAM
CY62128ELL-45SXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, PLASTIC, SOIC-32

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