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CY29775AXIT PDF预览

CY29775AXIT

更新时间: 2024-11-12 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路
页数 文件大小 规格书
11页 298K
描述
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer

CY29775AXIT 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP,针数:52
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74其他特性:ALSO OPERATES WITH 3.3V SUPPLY
系列:29775输入调节:MUX
JESD-30 代码:S-PQFP-G52长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:52
实输出次数:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:10 mm
最小 fmax:100 MHzBase Number Matches:1

CY29775AXIT 数据手册

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CY29775  
2.5V or 3.3V, 200-MHz, 14 Output Zero  
Delay Buffer  
Features  
Description  
Output frequency range: 8.3 MHz to 200 MHz  
Input frequency range: 4.2 MHz to 125 MHz  
2.5V or 3.3V operation  
The CY29775 is a low-voltage high-performance 200-MHz  
PLL-based zero delay buffer designed for high-speed clock  
distribution applications.  
The CY29775 features two reference clock inputs and provides  
14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A  
and Bank B divide the VCO output by 4 or 8 while Bank C divides  
by 8 or 12 per SEL(A:C) settings, see Function Table (Bank A,  
B, and C) on page 4. These dividers allow output to input ratios  
of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS  
compatible output can drive 50Ω series or parallel terminated  
transmission lines. For series terminated transmission lines,  
each output can drive one or two traces giving the device an  
effective fanout of 1:28.  
Split 2.5V/3.3V outputs  
14 Clock outputs: Drive up to 28 clock lines  
1 Feedback clock output  
2 LVCMOS reference clock inputs  
150 ps max output-output skew  
PLL bypass mode  
The PLL is ensured stable given that the VCO is configured to  
run between 200 MHz to 500 MHz. This allows a wide range of  
output frequencies from 8.3 MHz to 200 MHz. For normal  
operation, the external feedback input, FB_IN, is connected to  
the feedback output, FB_OUT. The internal VCO is running at  
multiples of the input reference clock set by the feedback divider,  
see Frequency Table on page 4.  
Spread Aware™  
Output enable/disable  
Industrial temperature range: –40°C to +85°C  
52-Pin 1.0-mm TQFP package  
When PLL_EN is LOW, PLL is bypassed and the reference clock  
directly feeds the output dividers. This mode is fully static and the  
minimum input clock frequency specification does not apply.  
Block Diagram  
VCO_SEL(1,0)  
PLL_EN  
TCLK_SEL  
TCLK0  
TCLK1  
PLL  
200 -  
500MHz  
CLK  
STOP  
÷2  
QA0  
÷2  
/ ÷4  
÷4  
QA1  
QA2  
QA3  
QA4  
FB_IN  
SELA  
CLK  
STOP  
÷2  
/ ÷4  
QB0  
QB1  
QB2  
QB3  
QB4  
SELB  
CLK  
STOP  
÷4  
/ ÷6  
QC0  
QC1  
QC2  
QC3  
SELC  
CLK_STP#  
FB_OUT  
÷4  
/
÷6  
/
÷8  
/
÷12  
FB_SEL(1,0)  
MR#/OE  
Cypress Semiconductor Corporation  
Document #: 38-07480 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 19, 2007  
[+] Feedback  

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