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CY29942AXI

更新时间: 2024-11-04 12:59:47
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赛普拉斯 - CYPRESS 时钟
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CY29942AXI 数据手册

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42  
CY29942  
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer  
Features  
Description  
• 200-MHz clock support  
• 2.5V or 3.3V operation  
The CY29942 is a low-voltage 200-MHz clock distribution buff-  
er with an LVCMOS or LVTTL compatible input clock. All other  
control inputs are LVCMOS/LVTTL compatible. The eighteen  
outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and  
can drive 50 series or parallel terminated transmission lines.  
For series terminated transmission lines, each output can  
drive one or two traces giving the devices an effective fanout  
of 1:36. Low output-to-output skews make the CY29942 an  
ideal clock distribution buffer for nested clock trees in the most  
demanding of synchronous systems.  
• LVCMOS/LVTTL clock input  
• LVCMOS-/LVTTL-compatible inputs  
• 18 clock outputs: drive up to 36 clock lines  
• 200 ps max. output-to-output skew  
• Output Enable control  
• Pin compatible with MPC942C  
Available in Industrial and Commercial  
32-pin LQFP package  
Block Diagram  
Pin Configuration  
VDD  
VSS  
VSS  
TCLK  
NC  
OE  
NC  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q6  
Q7  
Q8  
VDD  
Q9  
Q10  
Q11  
VSS  
18  
TCLK  
Q0-Q17  
CY29942  
OE  
VDD  
VDD  
Cypress Semiconductor Corporation  
Document #: 38-07284 Rev. *B  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised December 21, 2002  

CY29942AXI 替代型号

型号 品牌 替代类型 描述 数据表
CY29942AXIT CYPRESS

完全替代

Low Skew Clock Driver, 29942 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X
CY29940AXCT CYPRESS

类似代替

2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
CY29940AXI CYPRESS

功能相似

2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

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LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1 MM HEI