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CY29943AI

更新时间: 2024-11-25 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
7页 188K
描述
2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer

CY29943AI 数据手册

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CY29943  
2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer  
Features  
Description  
• 200-MHz clock support  
• 2.5V or 3.3V operation  
• LVPECL clock input  
The CY29943 is a low-voltage 200-MHz clock distribution  
buffer with an LVPECL-compatible input clock. All other control  
inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs  
are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can  
drive 50series or parallel terminated transmission lines. For  
series terminated transmission line, each output can drive one  
or two traces giving the device an effective fanout of 1:36. Low  
output-to-output skews make the CY29943 an ideal clock  
distribution buffer for nested clock trees in the most  
demanding of synchronous systems.  
• LVCMOS-/LVTTL-compatible inputs  
• 18 clock outputs: drive up to 36 clock lines  
• 200 ps max. output-to-output skew  
• Output Enable control  
• Pin compatible with MPC942P  
• Available in Industrial and Commercial  
• 32-pin LQFP package  
Block Diagram  
Pin Configuration  
VSS  
VSS  
OE  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q6  
Q7  
Q8  
VDD  
Q9  
Q10  
Q11  
VSS  
VDD  
NC  
18  
PECL_CLK  
PECL_CLK#  
CY29943  
PECL_CLK  
PECL_CLK#  
VDD  
Q0-Q17  
OE  
VDD  
Cypress Semiconductor Corporation  
Document #: 38-07285 Rev. *C  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised December 21, 2002  

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