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CY2546QCT

更新时间: 2024-11-18 19:45:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路晶体
页数 文件大小 规格书
19页 568K
描述
Clock Generator, 166MHz, CMOS, QFN-24

CY2546QCT 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.74
JESD-30 代码:S-XQCC-N24长度:4 mm
端子数量:24最高工作温度:70 °C
最低工作温度:最大输出时钟频率:166 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
主时钟/晶体标称频率:48 MHz座面最大高度:1 mm
最大供电电压:1.95 V最小供电电压:1.65 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY2546QCT 数据手册

 浏览型号CY2546QCT的Datasheet PDF文件第2页浏览型号CY2546QCT的Datasheet PDF文件第3页浏览型号CY2546QCT的Datasheet PDF文件第4页浏览型号CY2546QCT的Datasheet PDF文件第5页浏览型号CY2546QCT的Datasheet PDF文件第6页浏览型号CY2546QCT的Datasheet PDF文件第7页 
CY2544  
CY2546  
CY2548  
Quad PLL Programmable Clock Generator  
with Spread Spectrum  
Quad PLL Programmable Clock Generator with Spread Spectrum  
Up to nine clock outputs with programmable drive strength  
Glitch free outputs while frequency switching  
Features  
Four fully integrated phase locked loops (PLLs)  
24-pin QFN package  
Input frequency range  
Commercial and Industrial temperature ranges  
External crystal: 8 to 48 MHz for CY2544 and CY2546  
External reference: 8 to 166 MHz clock  
Benefits  
Reference clock input voltage range  
2.5 V, 3.0 V, and 3.3 V for CY2548  
1.8 V for CY2544 and CY2546  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
Programmable spread spectrum with center and down spread  
option and Lexmark and Linear modulation profiles  
Application specific programmable EMI reduction using spread  
spectrum for clocks  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548  
1.8 V for CY2546  
Programmable PLLs for system frequency margin tests  
Meets critical timing requirements in complex system designs  
Selectable output clock voltages:  
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548  
1.8 V for CY2546  
Suitability for PC, consumer, portable, and networking  
applications  
Capable of Zero PPM frequency synthesis error  
Frequency select feature with option to select eight different  
frequencies over nine clock outputs  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low power systems  
Power down, output enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
Functional Description  
Abilitytosynthesizenonstandard frequencies with Fractional-N  
capability  
For a complete list of related documentation, click here.  
Logic Block Diagram  
CLKIN  
CLK1  
Crossbar  
XIN/  
EXCLKIN  
Bank  
1
CLK2  
Switch  
OSC  
Output  
PLL1  
PLL2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
XOUT  
Dividers  
and  
Bank  
2
MUX  
and  
Drive  
FS 0  
FS 1  
FS 2  
Strength  
Control  
Bank  
3
Control  
Logic  
PLL3  
(SS)  
PLL4  
(SS)  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document Number: 001-12563 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 6, 2016  

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