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CY2547QI PDF预览

CY2547QI

更新时间: 2024-11-19 14:51:11
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
22页 503K
描述
8-Output Low-Voltage Programmable Spread Spectrum Clock Generator

CY2547QI 数据手册

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CY2545/CY2547  
Quad-PLL Programmable Spread Spectrum  
Clock Generator with Serial I2C Interface  
Quad-PLL Programmable Spread Spectrum Clock Generator with Serial I2  
C Interface  
24-pin QFN package  
Features  
Commercial and industrial temperature ranges  
Four fully-integrated phase-locked loops (PLLs)  
One-time programmability  
For programming support, contact Cypress technical support  
or send an e-mail to clocks@cypress.com  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Benefits  
Wide operating output frequency range  
3 to 166 MHz  
Serial programmable over two-wire I2C interface  
Multiple high-performance PLLs allow synthesis of unrelated  
frequencies  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
Programmable spread spectrum with center and down spread  
option and Lexmark and Linear modulation profiles  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY2545  
1.8 V for CY2547  
Application-specificprogrammable EMIreductionusing spread  
spectrum for clocks  
Programmable PLLs for system frequency margin tests  
Selectable output clock voltages independent of VDD supply:  
1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2545  
1.8 V for CY2547  
Meets critical timing requirements in complex system designs  
Suitability for PC, consumer, portable, and networking  
Power-down, output enable, or frequency select features  
Low jitter, high accuracy outputs  
applications  
Capable of zero PPM frequency synthesis error  
Ability tosynthesizenonstandard frequencies with Fractional-N  
capability  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low-power systems  
Up to eight clock outputs with programmable drive strength  
Glitch-free outputs while frequency switching  
Functional Description  
For a complete list of related documentation, click here.  
Logic Block Diagram  
CLKIN/RST  
Crossbar  
Switch  
CLK1  
XIN/  
EXCLKIN  
Bank  
1
CLK2  
Output  
OSC  
PLL1  
PLL2  
XOUT  
Dividers  
and  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
Bank  
2
Drive  
Strength  
Control  
MUX  
and  
FS  
Control  
Logic  
Bank  
3
PLL3  
(SS)  
SCL  
SDA  
PLL4  
(SS)  
I2C  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document Number: 001-13196 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 2, 2017  

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