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CY25483SXIT

更新时间: 2024-11-18 09:41:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
14页 245K
描述
Three PLL Programmable Clock Generator with Spread Spectrum

CY25483SXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.19
其他特性:IT CAN ALSO OPERATES ON 3 OR 3.3 V SUPPLYJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.889 mm
湿度敏感等级:3端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:166 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
主时钟/晶体标称频率:48 MHz认证状态:Not Qualified
座面最大高度:1.727 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:2.25 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.8985 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY25483SXIT 数据手册

 浏览型号CY25483SXIT的Datasheet PDF文件第2页浏览型号CY25483SXIT的Datasheet PDF文件第3页浏览型号CY25483SXIT的Datasheet PDF文件第4页浏览型号CY25483SXIT的Datasheet PDF文件第5页浏览型号CY25483SXIT的Datasheet PDF文件第6页浏览型号CY25483SXIT的Datasheet PDF文件第7页 
CY25403/CY25423/CY25483  
Three PLL Programmable Clock Generator  
with Spread Spectrum  
Features  
Three fully integrated phase-locked loops (PLLs)  
Three clock outputs with programmable drive strength  
Glitch-free outputs while frequency switching  
8-pin SOIC package  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Commercial and Industrial temperature ranges  
Reference clock input voltage range  
1.8 V for CY25403/CY25423/CY25483  
Benefits  
Wide operating output frequency range  
3 to 166 MHz  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Programmable spread spectrum with center and down spread  
option and lexmark and linear modulation profiles  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483  
ApplicationspecificprogrammableEMIreductionusingSpread  
Spectrum for clocks  
Selectable output clock voltages independent of VDD supply:  
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483  
Programmable PLLs for system frequency margin tests  
Frequency select feature with option to select four different  
frequencies  
Meets critical timing requirements in complex system designs  
Suitability for PC, consumer, portable, and networking  
applications  
Power-down, output enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
Capable of Zero PPM frequency synthesis error  
AbilitytosynthesizenonstandardfrequencieswithFractional-N  
capability  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low power systems  
Block Diagram  
Crossbar  
Switch  
XIN/  
EXCLKIN  
CLK1  
(SS)  
Output  
OSC  
PLL1  
XOUT  
Dividers  
and  
MUX  
and  
CLK2  
(No SS)  
Drive  
PLL 2  
(SS)  
FS0  
FS1  
Strength  
Control  
Control  
Logic  
CLK3  
(SS)  
PLL3  
(SS)  
SSON  
PD#/OE  
Cypress Semiconductor Corporation  
Document #: 001-12564 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 18, 2011  

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