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CY2548QI

更新时间: 2024-11-19 11:14:03
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟外围集成电路晶体
页数 文件大小 规格书
17页 487K
描述
9-Output Low-Voltage Programmable Spread Spectrum Clock Generator

CY2548QI 数据手册

 浏览型号CY2548QI的Datasheet PDF文件第2页浏览型号CY2548QI的Datasheet PDF文件第3页浏览型号CY2548QI的Datasheet PDF文件第4页浏览型号CY2548QI的Datasheet PDF文件第5页浏览型号CY2548QI的Datasheet PDF文件第6页浏览型号CY2548QI的Datasheet PDF文件第7页 
CY2544/CY2546/CY2548  
Quad-PLL Programmable Clock Generator  
with Spread Spectrum  
Quad-PLL Programmable Clock Generator with Spread Spectrum  
Glitch free outputs while frequency switching  
24-pin QFN package  
Features  
Four fully-integrated phase-locked loops (PLLs)  
Commercial and Industrial temperature ranges  
Input frequency range  
One-time programmability  
For programming support, contact Cypress technical support  
or send an e-mail to clocks@cypress.com  
External crystal: 8 to 48 MHz for CY2544 and CY2546  
External reference: 8 to 166 MHz clock  
Reference clock input voltage range  
2.5 V, 3.0 V, and 3.3 V for CY2548  
1.8 V for CY2544 and CY2546  
Benefits  
Multiple high-performance PLLs allow synthesis of unrelated  
frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
Programmable spread spectrum with center and down spread  
option and Lexmark and Linear modulation profiles  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548  
1.8 V for CY2546  
Application specific programmable EMI reduction using spread  
spectrum for clocks  
Programmable PLLs for system frequency margin tests  
Selectable output clock voltages:  
1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548  
1.8 V for CY2546  
Meets critical timing requirements in complex system designs  
Suitability for PC, consumer, portable, and networking  
applications  
Frequency select feature with option to select eight different  
frequencies over nine clock outputs  
Capable of Zero PPM frequency synthesis error  
Power down, output enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low-power systems  
Ability tosynthesizenonstandard frequencies with Fractional-N  
capability  
Functional Description  
For a complete list of related documentation, click here.  
Up to nine clock outputs with programmable drive strength  
Logic Block Diagram  
CLKIN  
CLK1  
Crossbar  
XIN/  
EXCLKIN  
Bank  
1
CLK2  
Switch  
OSC  
Output  
PLL1  
PLL2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
XOUT  
Dividers  
and  
Bank  
2
MUX  
and  
Drive  
FS 0  
FS 1  
FS 2  
Strength  
Control  
Bank  
3
Control  
Logic  
PLL3  
(SS)  
PLL4  
(SS)  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document Number: 001-12563 Rev. *M  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 31, 2017  

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