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CY25482SXC-XXX

更新时间: 2024-11-21 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
10页 259K
描述
Two PLL Programmable Clock Generator with Spread Spectrum

CY25482SXC-XXX 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.18
Is Samacsys:N其他特性:IT CAN ALSO OPERATES ON 3 OR 3.3 V SUPPLY
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.889 mm湿度敏感等级:3
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:166 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2.5/3.3 V主时钟/晶体标称频率:48 MHz
认证状态:Not Qualified座面最大高度:1.727 mm
子类别:Clock Generators最大供电电压:3.6 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3.8985 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY25482SXC-XXX 数据手册

 浏览型号CY25482SXC-XXX的Datasheet PDF文件第2页浏览型号CY25482SXC-XXX的Datasheet PDF文件第3页浏览型号CY25482SXC-XXX的Datasheet PDF文件第4页浏览型号CY25482SXC-XXX的Datasheet PDF文件第5页浏览型号CY25482SXC-XXX的Datasheet PDF文件第6页浏览型号CY25482SXC-XXX的Datasheet PDF文件第7页 
CY25402/CY25422/CY25482  
Two PLL Programmable Clock Generator  
with Spread Spectrum  
Three clock outputs with Programmable drive strength  
Glitch-free outputs while frequency switching  
8-pin SOIC package  
Features  
Two fully integrated phase locked loops (PLLs)  
Input frequency range  
Commercial and Industrial temperature ranges  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Benefits  
Reference Clock input voltage range  
2.5V, 3.0V, and 3.3V for CY25482  
1.8V for CY25402 and CY25422  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Nonvolatile programming for personalization of PLL  
frequencies,spreadspectrumcharacteristics,drivestrength,  
crystal load capacitance, and output frequencies  
Programmable Spread Spectrum with Center and Down  
Spread option and Lexmark and Linear modulation profiles  
Application specific Programmable EMI reduction using  
Spread Spectrum for clocks  
VDD supply voltage options:  
2.5V, 3.0V, and 3.3V for CY25402 and CY25482  
1.8V for CY25422  
Programmable PLLs for system frequency margin tests  
Meets critical timing requirements in complex system  
designs  
Selectable output clock voltages independent of VDD:  
2.5V, 3.0V, and 3.3V for CY25402 and CY25482  
1.8V for CY25422  
Suitability for PC, consumer, portable, and networking appli-  
cations  
Frequency Select feature with option to select four different  
frequencies  
Capable of Zero PPM frequency synthesis error  
Uninterrupted system operation during clock frequency  
Power Down, Output Enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
switch  
Application compatibility in standard and low power systems  
Ability to synthesize nonstandard frequencies with  
Fractional-N capability  
Block Diagram  
Crossbar  
XIN/  
CLK1  
Output  
Switch  
EXCLKIN  
PLL 1  
(SS)  
OSC  
Dividers  
and  
XOUT  
MUX  
and  
REFOUT  
CLK2  
Drive  
PLL 2  
(SS)  
Control  
Logic  
Strength  
Control  
FS0  
FS1  
SSON  
PD#/OE  
Cypress Semiconductor Corporation  
Document #: 001-12565 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 13, 2007  
[+] Feedback  

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