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CY25482SXIT

更新时间: 2024-11-06 14:56:07
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 293K
描述
3-Output Programmable Spread Spectrum Clock Generator

CY25482SXIT 数据手册

 浏览型号CY25482SXIT的Datasheet PDF文件第2页浏览型号CY25482SXIT的Datasheet PDF文件第3页浏览型号CY25482SXIT的Datasheet PDF文件第4页浏览型号CY25482SXIT的Datasheet PDF文件第5页浏览型号CY25482SXIT的Datasheet PDF文件第6页浏览型号CY25482SXIT的Datasheet PDF文件第7页 
CY25402/CY25422/CY25482  
Two-PLL Programmable Clock Generator  
with Spread Spectrum  
Two-PLL Programmable Clock Generator with Spread Spectrum  
8-pin small outline integrated circuit (SOIC) package  
Commercial and industrial temperature ranges  
Features  
Two fully integrated phase-locked loops (PLLs)  
One-time programmability  
For programming support, contact Cypress technical support  
or send an e-mail to clocks@cypress.com  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Benefits  
Reference clock input voltage range  
2.5 V, 3.0 V, and 3.3 V for CY25482  
1.8 V for CY25402 and CY25422  
Multiple high-performance PLLs allow synthesis of unrelated  
frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Programmable[1] spread spectrum with center and down  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
spread option and lexmark and linear modulation profiles  
Application specific programmableEMIreduction usingspread  
spectrum for clocks  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482  
1.8 V for CY25422  
Programmable PLLs for system frequency margin tests  
Meets critical timing requirements in complex system designs  
Frequency select feature with option to select four different  
frequencies  
Suitability for PC, consumer, portable, and networking  
applications  
Power-down, Output Enable, and SS ON/OFF controls  
Low jitter, high-accuracy outputs  
Capable of zero parts per million (PPM) frequency synthesis  
error  
Ability to synthesize nonstandard frequencies with fractional-N  
capability  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low-power systems  
Three clock outputs with programmable drive strength  
Glitch-free outputs while frequency switching  
Functional Description  
For a complete list of related documentation, click here.  
Block Diagram  
XIN  
Crossbar  
Switch  
CLK1  
(SS)  
/
Output  
EXCLKIN  
PLL 1  
(SS)  
XOU  
T
OSC  
Dividers  
and  
MU  
X
REFOUT  
(No SS)  
Drive  
and  
Control  
Logic  
PLL 2  
(SS)  
Strength  
Control  
FS0  
FS1  
CLK2  
(SS)  
SSON  
PD#/OE  
Note  
1. The devices mentioned in this datasheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming software  
is currently not available. Visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches your  
requirements.  
Cypress Semiconductor Corporation  
Document Number: 001-12565 Rev. *M  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 31, 2017  

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