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CY2547

更新时间: 2024-11-18 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
15页 334K
描述
Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface

CY2547 数据手册

 浏览型号CY2547的Datasheet PDF文件第2页浏览型号CY2547的Datasheet PDF文件第3页浏览型号CY2547的Datasheet PDF文件第4页浏览型号CY2547的Datasheet PDF文件第5页浏览型号CY2547的Datasheet PDF文件第6页浏览型号CY2547的Datasheet PDF文件第7页 
CY2545  
CY2547  
Quad PLL Programmable Spread Spectrum  
2
Clock Generator with Serial I C Interface  
Glitch-free outputs while frequency switching  
24-pin QFN package  
Features  
Four fully integrated phase locked loops (PLLs)  
Commercial and industrial temperature ranges  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Benefits  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Nonvolatile programming for personalization of PLL  
frequencies,spreadspectrumcharacteristics,drivestrength,  
Serial programmable over 2-wire I2C interface  
crystal load capacitance, and output frequencies  
Programmable spread spectrum with center and down  
spread option and Lexmark and Linear modulation profiles  
Application specific programmable EMI reduction using  
Spread Spectrum for clocks  
VDD supply voltage options:  
2.5V, 3.0V, and 3.3V for CY2545  
1.8V for CY2547  
Programmable PLLs for system frequency margin tests  
Meets critical timing requirements in complex system  
designs  
Selectable output clock voltages independent of VDD supply:  
2.5V, 3.0V, and 3.3V for CY2545  
1.8V for CY2547  
Suitability for PC, consumer, portable, and networking appli-  
cations  
Power down, output enable, or frequency select features  
Low jitter, high accuracy outputs  
Capable of Zero PPM frequency synthesis error  
Uninterrupted system operation during clock frequency  
switch  
Ability to synthesize nonstandard frequencies with  
Fractional-N capability  
Application compatibility in standard and low power systems  
Up to eight clock outputs with programmable drive strength  
Logic Block Diagram  
CLKIN/RST  
Crossbar  
Switch  
CLK1  
XIN/  
EXCLKIN  
Bank  
1
CLK2  
Output  
OSC  
PLL1  
XOUT  
Dividers  
and  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
Bank  
2
Drive  
PLL2  
Strength  
Control  
MUX  
and  
Control  
Logic  
FS  
Bank  
3
PLL3  
(SS)  
SCL  
SDA  
PLL4  
(SS)  
I2C  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document #: 001-13196 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 05, 2007  
[+] Feedback  

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