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CY2546IT

更新时间: 2024-11-18 13:00:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
11页 317K
描述
暂无描述

CY2546IT 数据手册

 浏览型号CY2546IT的Datasheet PDF文件第2页浏览型号CY2546IT的Datasheet PDF文件第3页浏览型号CY2546IT的Datasheet PDF文件第4页浏览型号CY2546IT的Datasheet PDF文件第5页浏览型号CY2546IT的Datasheet PDF文件第6页浏览型号CY2546IT的Datasheet PDF文件第7页 
CY2544  
CY2546  
PRELIMINARY  
Quad PLL Programmable Clock Generator with  
Spread Spectrum  
Features  
Benefits  
• Multiple high-performance PLLs allow synthesis of  
unrelated frequencies  
• Four fully integrated phase-locked loops (PLLs)  
• Input Frequency range:  
• Nonvolatile programming for customized PLL frequencies,  
spreadspectrumcharacteristics, drivestrength,crystalload  
capacitance, and output frequencies  
— External crystal: 8 to 48 MHz  
— External reference: 8 to 166 MHz clock  
• Wide operating output frequency range  
— 3 to 166 MHz  
• TwoSpreadSpectrumcapablePLLswithLinearorLexmark  
profile for maximum EMI reduction  
• Spread Spectrum PLLs can be disabled or enabled  
separately  
• Programmable Spread Spectrum with Center and Down  
Spread option and Lexmark modulation profile  
• PLLs can be programmed for system frequency margin  
tests  
• Two VDD core voltage options:  
— 2.5V, 3.0V, and 3.3V for CY2544  
— 1.8V for CY2546  
• Meets critical timing requirements in complex system  
designs  
• Suitable for PC, consumer, and networking applications  
• Ability to synthesize standard frequencies with ease  
• Selectable output voltages:  
— 2.5V, 3.0V, and 3.3V for CY2544  
— 1.8V for CY2546  
• Application compatibility in standard and low-power  
systems  
• FrequencySelectfeaturewithoptiontoselecteightdifferent  
frequencies  
• Low jitter, high accuracy outputs  
• Up to nine clock outputs  
• Programmable output drive strength  
• Glitch-free outputs while frequency switching  
• 24-pin QFN package  
• Commercial and Industrial temperature ranges  
Block Diagram  
EXCLKIN  
4 of 6  
Crossbar  
Switch  
CLK1  
CLK2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
Bank  
1
XIN  
Output  
OSC  
PLL1  
XOUT  
Dividers  
and  
Bank  
2
Drive  
FS0  
FS1  
FS2  
PLL2  
Strength  
MUX  
and  
Control  
Logic  
Control  
Bank  
3
PLL3  
(SS)  
PLL4  
(SS)  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document #: 001-12563 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 28, 2007  
[+] Feedback  

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