Datasheet > CY24142-01

CY24142-01

更新时间： 2024-11-23 22:40:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
7页	130K
描述
MediaClock Multimedia Clock Generator

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中文翻译

获取价格

数据手册

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CY24142-01 数据手册

CY24142

MediaClock™

Multimedia Clock Generator

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• 3.3V operation

• Integrated high-performance PLL eliminates the need for

— external loop filter components

• Meets critical timing requirements in complex system

designs

• Enables application compatibility

Logic Block Diagram

XIN

OSC.

VCO

OUTPUT

XOUT

MULTIPLEXER

CLK1 13.5 MHz

CLK2 54 MHz

AND

DIVIDERS

PLL

CLK3 18.432 MHz

CLK4 18.432 MHz

OE1

OE2

VSS

AVDD AVSS

VDDL

VDD

VSSL

Pin Configuration

CY24142

16-pin TSSOP

XOUT

XIN

VDD

AVDD

CLK4

CLK3

VSS

OE1

AVSS

VSSL

VDDL

OE2

CLK2

CLK1

Frequency Table

Part Number Outputs

Input Frequency

Output Frequency Range

13.5 MHz, 54 MHz, 2 x 18.432 MHz

CY24142-01

18.432

Output Enable Options^[1]

OE2

OE1

CLK1

13.5

CLK2

OFF

CLK3

OFF

18.432

OFF

CLK4

OFF

18.432

Unit

MHz

18.432

Note:

1. Output driven LOW when “OFF.”

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07532 Rev. *B

Revised January 19, 2005

12 3 4 5 6 7

中文翻译

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