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CY241V08A-12 PDF预览

CY241V08A-12

更新时间: 2024-11-24 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器石英晶振压控振荡器
页数 文件大小 规格书
6页 122K
描述
Clock Generator with VCXO

CY241V08A-12 数据手册

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CY241V08A-12  
Clock Generator with VCXO  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
• Highest-performance PLL tailored for multimedia  
applications  
• Meets critical timing requirements in complex system  
designs  
Application compatibility for a wide variety of designs  
Frequency Table  
VCXO Control  
Part Number Outputs  
Input Frequency Range  
Output Frequencies  
One copy of 27 MHz  
One copy of 74.25 MHz  
Curve  
CY241V08A-12  
2
27-MHz pullable crystal input per  
linear  
Cypress specification  
Block Diagram  
OUTPUT  
DIVIDER  
PLL  
74.25MHz  
27 XIN  
XOUT  
XBUF/27MHz  
OSC  
VCXO  
VSS  
VDD  
Pin Configuration  
CY241V08A-12  
8-pin SOIC  
XOUT  
1
2
3
4
8
7
6
5
XIN  
NC  
74.25 MHz  
VDD  
VCXO  
VSS  
XBUF/27 MHz  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07676 Rev. **  
Revised June 02, 2004  

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