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CY241V08SC-06 PDF预览

CY241V08SC-06

更新时间: 2024-11-24 13:29:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 44K
描述
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

CY241V08SC-06 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:NJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.8895 mm
湿度敏感等级:1端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:27 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):220
主时钟/晶体标称频率:13.5 MHz认证状态:Not Qualified
座面最大高度:1.727 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.8989 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

CY241V08SC-06 数据手册

 浏览型号CY241V08SC-06的Datasheet PDF文件第2页浏览型号CY241V08SC-06的Datasheet PDF文件第3页浏览型号CY241V08SC-06的Datasheet PDF文件第4页浏览型号CY241V08SC-06的Datasheet PDF文件第5页浏览型号CY241V08SC-06的Datasheet PDF文件第6页 
CY241V08-01,-04,-05,-06  
PRELIMINARY  
MPEG Clock Generator with VCXO  
Features  
Advance Features  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
• Lower drive strength settings (CY241V08-04, -06)  
Benefits  
• Electromagnetic interference (EMI) reduction for standards  
compliance  
Benefits  
• Highest-performance PLL tailored for multimedia applica-  
tions  
• Meets critical timing requirements in complex system  
designs  
• Application compatibility for a wide variety of designs  
Frequency Table  
Part  
Number  
Output  
Frequencies  
VCXOControl  
Curve  
Outputs  
Input Frequency Range  
Other Features  
CY241V08-01  
1
13.5-MHz pullable crystal input One copy of 27 MHz linear  
per Cypress specification  
Pinout compatible with MK3727  
CY241V08-04  
CY241V08-05  
CY241V08-06  
1
1
1
13.5-MHz pullable crystal input One copy of 27 MHz linear  
per Cypress specification  
Same as CY241V08-01 except  
lower drive strength settings  
13.5-MHz pullable crystal input One copy of 27 MHz nonlinear  
per Cypress specification  
Mimics MK3727 nonlinear  
VCXO Control Curve  
13.5-MHz pullable crystal input One copy of 27 MHz nonlinear  
per Cypress specification  
Same as CY241V08-05 except  
lower drive strength settings  
Block Diagram  
OUTPUT  
DIVIDER  
13.5 XIN  
XOUT  
PLL  
OSC  
27 MHz  
VCXO  
VSS  
VDD  
Pin Configuration  
CY241V08-01,-04,-05,-06  
8-pin SOIC  
1
2
3
4
XOUT  
8
7
6
5
XIN  
NC or VSS  
NC or VDD  
27 MHz  
VDD  
VCXO  
VSS  
Cypress Semiconductor Corporation  
Document #: 38-07520 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised July 28, 2003  

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