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CY24204 PDF预览

CY24204

更新时间: 2024-11-24 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器电视
页数 文件大小 规格书
6页 137K
描述
MediaClock⑩ DTV, STB Clock Generator

CY24204 数据手册

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CY24204  
MediaClock™  
DTV, S
TB Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low jitter, high-accuracy outputs  
• VCXO with Analog Adjust  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Large ±150-ppm range, better linearity  
• Enables application compatibility  
Part Number Outputs  
Input Frequency  
Output Frequency Range  
CY24204-3  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable)  
CY24204-4  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased VCXO pull range)  
CY24204-5  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased output drive strength)  
Pin Configurations  
Block Diagram  
16-pin TSSOP  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
XOUT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
XIN  
VDD  
AVDD  
MULTIPLEXER  
AND  
CLK1  
CLK2  
OE  
FS1  
VSS  
CLK1  
VDDL  
P
VCXO  
DIVIDERS  
PLL  
VCXO  
AVSS  
VSSL  
REFCLK1  
11  
10  
REFCLK2  
(-3,-4,-5)  
REFCLK2  
REFCLK1  
FS0  
CLK2  
FS0  
FS1  
OE  
9
VSSL  
VSS  
VDD  
AVDD AVSS  
VDDL  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07450 Rev. *C  
Revised January 19, 2005  

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