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CY24204ZC-3T PDF预览

CY24204ZC-3T

更新时间: 2024-11-27 03:02:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路电视光电二极管
页数 文件大小 规格书
6页 137K
描述
MediaClock⑩ DTV, STB Clock Generator

CY24204ZC-3T 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, MO-153, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.8Is Samacsys:N
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm湿度敏感等级:1
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:74.25 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
电源:3.3 V主时钟/晶体标称频率:27 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Clock Generators最大压摆率:25 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

CY24204ZC-3T 数据手册

 浏览型号CY24204ZC-3T的Datasheet PDF文件第2页浏览型号CY24204ZC-3T的Datasheet PDF文件第3页浏览型号CY24204ZC-3T的Datasheet PDF文件第4页浏览型号CY24204ZC-3T的Datasheet PDF文件第5页浏览型号CY24204ZC-3T的Datasheet PDF文件第6页 
CY24204  
MediaClock™  
DTV, S
TB Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low jitter, high-accuracy outputs  
• VCXO with Analog Adjust  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Large ±150-ppm range, better linearity  
• Enables application compatibility  
Part Number Outputs  
Input Frequency  
Output Frequency Range  
CY24204-3  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable)  
CY24204-4  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased VCXO pull range)  
CY24204-5  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased output drive strength)  
Pin Configurations  
Block Diagram  
16-pin TSSOP  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
XOUT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
XIN  
VDD  
AVDD  
MULTIPLEXER  
AND  
CLK1  
CLK2  
OE  
FS1  
VSS  
CLK1  
VDDL  
P
VCXO  
DIVIDERS  
PLL  
VCXO  
AVSS  
VSSL  
REFCLK1  
11  
10  
REFCLK2  
(-3,-4,-5)  
REFCLK2  
REFCLK1  
FS0  
CLK2  
FS0  
FS1  
OE  
9
VSSL  
VSS  
VDD  
AVDD AVSS  
VDDL  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07450 Rev. *C  
Revised January 19, 2005  

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