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CY24206ZXC-4T PDF预览

CY24206ZXC-4T

更新时间: 2024-11-21 19:53:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 137K
描述
Video Clock Generator, 81.081MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

CY24206ZXC-4T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, LEAD FREE, MO-153, TSSOP-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:3端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:81.081 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大压摆率:25 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

CY24206ZXC-4T 数据手册

 浏览型号CY24206ZXC-4T的Datasheet PDF文件第2页浏览型号CY24206ZXC-4T的Datasheet PDF文件第3页浏览型号CY24206ZXC-4T的Datasheet PDF文件第4页浏览型号CY24206ZXC-4T的Datasheet PDF文件第5页浏览型号CY24206ZXC-4T的Datasheet PDF文件第6页 
CY24206  
MediaClock™ DTV, STB Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
Output Frequency Range  
• Available in 16-pin TSSOP Package  
Part Number Outputs Input Frequency  
CY24206-1  
3
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
CY24206-2  
4
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
CY24206-3  
CY24206-4  
4
4
27 MHz  
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
Logic Block Diagram  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
MULTIPLEXER  
CLK1  
CLK2  
AND  
P
DIVIDERS  
PLL  
REFCLK  
FS0  
CLK3 (-2, -3,-4)  
FS1  
FS2  
OE  
VSS  
AVDD AVSS  
VDDL  
VDD  
VSSL  
Pin Configurations  
CY24206-2,3,4  
16-pin TSSOP  
CY24206-1  
16-pin TSSOP  
XOUT  
XOUT  
1
1
16  
16  
XIN  
VDD  
AVDD  
OE  
AVSS  
VSSL  
XIN  
15  
14  
13  
12  
15  
14  
13  
12  
2
3
4
5
6
7
8
2
3
4
5
6
FS2  
FS1  
VSS  
VDD  
AVDD  
OE  
AVSS  
VSSL  
FS2  
FS1  
VSS  
CLK3  
VDDL  
N/C  
VDDL  
11  
10  
11  
10  
7
8
FS0  
REFCLK  
FS0  
REFCLK  
CLK1  
CLK2  
CLK1  
CLK2  
9
9
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07451 Rev. *B  
Revised September 27, 2004  
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