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CY24206-4 PDF预览

CY24206-4

更新时间: 2024-11-27 09:41:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器电视
页数 文件大小 规格书
6页 132K
描述
MediaClock - TM DTV, STB Clock Generator

CY24206-4 数据手册

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CY24206  
MediaClock™ DTV, STB Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
Output Frequency Range  
• Available in 16-pin TSSOP Package  
Part Number Outputs Input Frequency  
CY24206-1  
3
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
CY24206-2  
4
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
CY24206-3  
CY24206-4  
4
4
27 MHz  
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
Logic Block Diagram  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
MULTIPLEXER  
CLK1  
CLK2  
AND  
P
DIVIDERS  
PLL  
REFCLK  
FS0  
CLK3 (-2, -3,-4)  
FS1  
FS2  
OE  
VSS  
AVDD AVSS  
VDDL  
VDD  
VSSL  
Pin Configurations  
CY24206-2,3,4  
16-pin TSSOP  
CY24206-1  
16-pin TSSOP  
XOUT  
XOUT  
1
1
16  
16  
XIN  
VDD  
AVDD  
OE  
AVSS  
VSSL  
XIN  
15  
14  
13  
12  
15  
14  
13  
12  
2
3
4
5
6
7
8
2
3
4
5
6
FS2  
FS1  
VSS  
VDD  
AVDD  
OE  
AVSS  
VSSL  
FS2  
FS1  
VSS  
CLK3  
VDDL  
N/C  
VDDL  
11  
10  
11  
10  
7
8
FS0  
REFCLK  
FS0  
REFCLK  
CLK1  
CLK2  
CLK1  
CLK2  
9
9
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07451 Rev. *B  
Revised September 27, 2004  

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