5秒后页面跳转
CY24207ZC-1 PDF预览

CY24207ZC-1

更新时间: 2024-11-20 22:06:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器光电二极管
页数 文件大小 规格书
6页 49K
描述
MediaClock PDP Clock Generator

CY24207ZC-1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
湿度敏感等级:1端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:67.425 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大压摆率:25 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

CY24207ZC-1 数据手册

 浏览型号CY24207ZC-1的Datasheet PDF文件第2页浏览型号CY24207ZC-1的Datasheet PDF文件第3页浏览型号CY24207ZC-1的Datasheet PDF文件第4页浏览型号CY24207ZC-1的Datasheet PDF文件第5页浏览型号CY24207ZC-1的Datasheet PDF文件第6页 
CY24207  
MediaClock™  
PDP Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• VCXO with Analog Adjust  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Large ±200-ppm range, better linearity  
• Enables application compatibility  
Part Number Outputs  
Input Frequency  
Output Frequency Range  
CY24207-1  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
54/53.946053/67.425/67.357642 MHz (frequency selectable)  
CY24207-2  
4
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
54/53.946053/67.425/68.400599 MHz (frequency selectable)  
Pin Configuration  
Block Diagram  
16-pin TSSOP  
XOUT  
1
2
3
4
5
6
16  
15  
14  
13  
12  
XIN  
XIN  
VDD  
Q
OSC.  
Φ
OE  
VCO  
OUTPUT  
MULTIPLEXER  
AND  
XOUT  
VCXO  
FS1  
VSS  
AVDD  
CLK1  
CLK2  
P
DIVIDERS  
VCXO  
CLK1  
VDDL  
AVSS  
VSSL  
PLL  
11  
10  
REFCLK1  
REFCLK2  
REFCLK2  
7
8
FS0  
9
REFCLK1  
CLK2  
FS0  
FS1  
OE  
VSSL  
VSS  
VDD  
AVDD AVSS  
VDDL  
Frequency Select Options  
OE  
0
FS1  
0
FS0  
0
CLK1/CLK2 (-1)[1]  
CLK1/CLK2 (-2)[1]  
REFCLK 1/2  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
off  
off  
27  
27  
27  
27  
27  
27  
27  
27  
0
0
1
off  
off  
0
1
0
off  
off  
0
1
1
off  
54  
off  
54  
1
0
0
1
0
1
53.946053 (–1 ppm)  
67.425  
53.946053 (–1 ppm)  
67.425  
1
1
0
1
1
1
67.357642 (3.8 ppm)  
68.400599(–8.8 ppm)  
Note:  
1. “off” = output is driven high.  
Cypress Semiconductor Corporation  
Document #: 38-07553 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised July 31, 2003  

与CY24207ZC-1相关器件

型号 品牌 获取价格 描述 数据表
CY24207ZC-1T CYPRESS

获取价格

MediaClock PDP Clock Generator
CY24207ZC-2 CYPRESS

获取价格

MediaClock PDP Clock Generator
CY24207ZC-2T CYPRESS

获取价格

MediaClock PDP Clock Generator
CY24210 ETC

获取价格

Clocks and Buffers
CY24210-3 CYPRESS

获取价格

Clock Generator, PDSO8,
CY24210-4 CYPRESS

获取价格

Clock Generator, PDSO8,
CY24210-5 CYPRESS

获取价格

Clock Generator, PDSO8,
CY24210-6 CYPRESS

获取价格

Clock Generator, PDSO8,
CY24210-7 CYPRESS

获取价格

Clock Generator, PDSO8,
CY24210SC-4T CYPRESS

获取价格

Clock Generator, 100MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8