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CY24212_05 PDF预览

CY24212_05

更新时间: 2024-11-21 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器石英晶振压控振荡器
页数 文件大小 规格书
6页 136K
描述
MediaClock⑩ MPEG Clock Generator with VCXO

CY24212_05 数据手册

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PRELIMINARY  
CY24212  
MediaClock™  
MPEG Clock Generator with VCXO  
Features  
• Integrated phase-locked loop (PLL)  
• Low jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
Benefits  
Highest-performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Large ±150-ppm range, better linearity  
Enables application compatibility  
Part Number Outputs  
Input Frequency Range  
13.5 MHz/27 MHz (selectable)  
13.5 MHz/27 MHz (selectable)  
Output Frequencies  
CY24212-1  
CY24212-2  
CY24212-3  
CY24212-5  
1
2
2
2
27 MHz  
Two copies of 27 MHz  
27 MHz/27.027 MHz (-1 ppm)  
27 MHz/27.027 MHz (0 ppm)  
27 MHz  
27 MHz  
Logic Block Diagram  
OUTPUT  
DIVIDERS  
XIN  
OSC  
Q
Φ
CLKA (27 MHz)  
XOUT  
VCO  
PLL  
27 MHz (-2)  
27/27.027 MHz (-3)  
P
VCXO  
FSEL  
VSS  
VDD  
Pin Configurations  
CY24212-3,-5  
8-pin SOIC  
CY24212-1  
8-pin SOIC  
CY24212-2  
8-pin SOIC  
XOUT  
1
XOUT  
8
1
XOUT  
1
XIN  
8
8
XIN  
XIN  
7
6
5
2
3
4
CLKB (27/27.027 MHz)  
FSEL  
CLKA 27 MHz  
7
6
5
2
3
4
VSS  
FSEL  
CLKA 27 MHz  
2
3
4
7
6
5
VDD  
VCXO  
VSS  
CLKB 27 MHz  
VDD  
VCXO  
VSS  
VDD  
VCXO  
VSS  
FSEL  
CLKA 27 MHz  
Table 1. CY24212 (-1, -2) Frequency Select Option  
FSEL  
0
1
Reference  
13.5 MHz  
27 MHz  
CLKA/CLKB  
27 MHz  
27 MHz  
Table 2. CY24212 (-3, -5) Frequency Select Option  
FSEL  
0
1
Reference  
27 MHz  
27 MHz  
CLKA  
27 MHz  
27 MHz  
CLKB  
27 MHz  
27.027 MHz  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07402 Rev. *C  
Revised April 6, 2005  

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